Document Number: 002-10689 Rev *H
Page 144 of 166
S6J32E, S6J32F, S6J32G Series
I2Sx_SCK
V
OH
V
OL
I2Sx_SD,
I2Sx_WS
(output timing)
V
OH
V
OL
t
dtr
t
hdr
t
sck
V
OH
V
OH
I2Sx_SD
(input timing)
V
IH
V
IH
V
IL
V
IL
t
hr
t
sr
t
shw
t
slw
V
OL
V
OL
8.4.23.2
I2S Timing
– Slave mode (MSMD=0)
Parameter
Symbol
Pin Name
Conditions
Value
Uni
t
Remarks
Min
Max
I2S clock cycle (input
SCK)
t
sck
I2S0_SCK,
I2S1_SCK
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
CPOL = 0,
SMPL = 0
66.66
-
ns
I2S clock “H” pulse
width
t
shw
I2S0_SCK,
I2S1_SCK
0.40*
t
sck
0.60*
t
sck
ns
I2S clock “L” pulse
width
t
slw
0.40*
t
sck
0.60*
t
sck
ns
Setup time
WS transition ->
SCK↓
t
srf
I2S0_SCK,
I2S1_SCK,
I2S0_WS,
I2S1_WS
40
-
ns
*1
Hold time
SCK↓ -> WS
transition
t
hrf
10
-
ns
*1
Sender delay time
SCK↑ -> SD valid
t
dtr
I2S0_SCK,
I2S1_SCK,
I2S0_SD,
I2S1_SD
-
35
ns
*1
Sender hold time
SCK↑ -> SD invalid
t
htr
-10
-
ns
*1
Receiver setup time
SD valid -
> SCK↓
t
sr
I2S0_SCK,
I2S1_SCK,
I2S0_SD,
I2S1_SD
40
-
ns
*1
Receiver hold time
SCK↓ -> SD valid
t
hr
10
-
ns
*1
Notes:
*1: Refer to the I2S register description chapter in the
for different combinations of clock polarity (CPOL), sampling point
position (SMPL), polarity/pulse_width/frame_sync phase of WS (FSPL, FSLN, FSPH). Actual waveforms and relevant clock
edges will change accordingly; the delay values listed in the previous table will remain the same.
