Cypress Traveo S6J32E Series Manual Download

Page: 161 / 167

Document Number: 002-10689 Rev *H

Page 161 of 166

S6J32E, S6J32F, S6J32G Series

Revision

ECN

Orig. of Change

Submission

Date

Description of Change

description about guaranteed MCU operation range, updated notes, removed

redundant LVDH0 spec

Section

3.2: section “PLL/SSCG PLL” in Table3-1: Center spread mode usage is

permitted (with conditions)

Section 8.4.3:Added note about SSCG center spread mode

Section 8.4.3: Added spec for Hyperbus VIH/VIL and VOH/VOL levels

Section 8.4.16: Added description about VIH/VIL and VOH/VOL

Section 7.2: Deleted note about

“Power-on Time”

Section 8.4.16.3 and 8.4.16.4: tDSS is setup time of “data-> clock “

Section 8.4.6.2: changed clock cycle time and H/L pulse width definitions (mainly

removed “Remarks”)

Section 8.4.8: removed spec for stop mode

Section 8.4.6.2 MFS: aligned font size in tables (different sizes were used in the

same table)

Section 8.3.2.1: added 50 MHz as condition for ILVDS of AVCC3_LVDS_PLL

Section 8.4.12.1/2/3 Display controller: revised method of specifying AC spec

Section 8.4.12.1/2/3 Display controller: Updated waveforms according to new AC

spec

Section 8.4.12.1/2 Display controller/DSP0: change max frequency from 80 MHz to

64 MHz to match guaranteed performance of Graphic subsystem

Section 8.4.6.3 MFS/CSIO: changed

SOVLI

and t

SOVHI

to 2x tclk

Section 8.4.6.2 (1)-(4) removed redundant information from t

SCYC

, t

SHSL

, t

SLSH

(1),(2)removed obsolete footnote *2 and changed footnote number *3 to *2

(3),(4) flipped footnote *2,*3 and updated footnote assignment at t

SOVLI

(3),(4) added SOT16, 17 to Pin name of

SOVLI

(8) added figure for t

SCC

Section 8.4.6.3 Lin Interface: corrected figure

Section 8.4.16 corrected cross reference

Section 8.4.10.5 corrected max value of LVDL2V=01

Section 3.2.1: RMII

– corrected usage of CRS (to 'not used'), RX_DV (to 'used')

Section 8.4.18.4: Ethernet RMII: AC: added RXDV and updated waveform for

adding RXDV and note below the table

Section 8.4.18.4: Moved IO-cell driving strength to output function only

5429050

ANMA

09/07/2016

Section 2.2.1/Figure 2-1: Options and Part numbers: added Option 'M' for revised

version.

Section 2.2.2: Added Chip-ID and JTAG-ID for Revision 'M'

Section 2.1 Function list: Graphic-TTL output/RSDS/FPD-link - added description

about which channel can be used on which output type

Section 2.1 Function list: Display clock

– corrected from 80 MHz to 64 MHz

Updated copyright information and added IoT link on the last page.

Summary of Contents for Traveo S6J32E Series

Page 1: ...nables the device to be used for many mid range graphics applications Features Key Features 240 MHz Arm Cortex R5F CPU 4 MB internal high speed Flash memory 512 KB RAM Supports 2 7 V to 5 5 V and 2 7 V to 3 6 V I O supply voltage 1 2 V core power supply 50 channel 12 bit SAR A D converter with 1 Msps conversion rate Embedded 4 channel CAN FD controller 12 channel Multi Function Serial MFS communic...

Page 2: ... 3 TEQFP 256 26 5 I O Circuit Type 27 5 1 I O Circuit Type 27 6 Port Description 34 6 1 Port Description List 34 6 2 Remark 54 7 Precautions and Handling Devices 54 7 1 Handling Precautions 54 7 1 1 Precautions for Product Design 54 7 1 2 Precautions for Package Mounting 55 7 1 3 Precautions for Use Environment 56 7 2 Handling Devices 57 8 Electric Characteristics 59 8 1 Absolute Maximum Rating 59...

Page 3: ... 16 DDR HSSPI 126 8 4 17 HyperBus 130 8 4 18 Ethernet AVB 134 8 4 19 MediaLB 137 8 4 20 Port Noise Filter 138 8 5 A D Converter 145 8 5 1 Electrical Characteristics 145 8 5 2 Notes on A D Converters 147 8 5 3 Glossary 147 8 5 4 Calibration Condition 147 8 6 Audio DAC 150 8 6 1 Electrical Characteristics 150 8 7 Flash Memory 153 8 7 1 Electrical Characteristics 153 8 7 2 Notes 153 9 Abbreviation 15...

Page 4: ...asheet Supplementary information for document such as differences with the previous revision Datasheet user NA Supplementary Hardware manual Supplementary information for document such as differences with the previous revision Hardware manual user NA Application notes Explanation of the reference software sample application the reference board design and so on Software and hardware engineer AN2098...

Page 5: ...G Available Data cache 16 KB Instruction cache 16 KB Program FLASH 4160 KB Work FLASH 112 KB TC RAM 128 KB System RAM 384 KB Backup RAM 16 KB Security SHE Option See 2 2 1 Low latency interrupt Available Power domain 5 domains Power supply 5 V 0 5 V 3 3 V 0 3 V 1 2 V 0 1 V Embedded LDO power supply for 5 0 V Available Low voltage detection of external power supply Available Low voltage detection o...

Page 6: ...ck 200 MHz Graphic AXI clock 200 MHz Display clock 64 MHz ch 0 50 MHz ch 1 Display clock source Graphic display controller clock or external clock Target frame rate 60 fps Number of display outputs Maximum 2 outputs simultaneously See 2 2 1 TTL output RGB888 2 ch Display channel ch 0 Display channel ch 1 RSDS TCON support 1 output Display channel ch 0 FPD Link LVDS 1 output 350 Mbps Max Display ch...

Page 7: ...FL0023 1 N 3rd revision added alternative location for RXDV on P5_27 fixed FL0027 1 Option Digit SHE Flash Chip erase S ON U OFF T ON V OFF Pin count Digit Pin count K 208 pin L 216 pin M 256 pin Memory size Digit Program FLASH Work FLASH TC RAM VRAM E 4160KB 112KB 128KB 2048KB Function See the function digit table Product series Digit Product type 2 Graphic SoC Identifier Automotive MCU 1 Please ...

Page 8: ...er Bus Interface ch no 0 1 0 1 0 1 2 Sound System OFF ON ON Notes This table only shows the relations between the optional function and the part numbers That is all products are not necessarily available for orders See the order number on the datasheet and confirm actual availability of products The sound system is composed of the sound waveform generator the sound mixer the audio DAC PCM PWM and ...

Page 9: ...tion Digit Memory Pin Count Option Revision Chip ID JTAG ID E E K S M 0x10150001 0x101035CF T 0x1010B5CF U 0x101135CF V 0x1011B5CF L S 0x101015CF T 0x101095CF U 0x101115CF V 0x101195CF F K S 0x101055CF T 0x1010D5CF U 0x101155CF V 0x1011D5CF L S 0x101045CF T 0x1010C5CF U 0x101145CF V 0x1011C5CF G K S 0x101025CF T 0x1010A5CF U 0x101125CF V 0x1011A5CF L S 0x101005CF T 0x101085CF U 0x101105CF V 0x1011...

Page 10: ...F T 0x2010D5CF U 0x201155CF V 0x2011D5CF L S 0x201045CF T 0x2010C5CF U 0x201145CF V 0x2011C5CF G K S 0x201025CF T 0x2010A5CF U 0x201125CF V 0x2011A5CF L S 0x201005CF T 0x201085CF U 0x201105CF V 0x201185CF M S 0x201065CF T 0x2010E5CF U 0x201165CF V 0x2011E5CF Note The JTAG ID is stored in a memory in the PD2 It can only be read after device startup VCC12 must be supplied and RSTX must be released 2...

Page 11: ...P1_06 P1_07 P1_08 P1_09 P2_16 P2_17 P2_19 P2_22 P2_24 P2_25 P2_26 P2_27 P2_28 P2_29 P2_30 P2_31 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P3_07 P3_08 P3_09 P3_10 P3_11 P3_12 P3_13 P3_14 P3_15 P3_16 P3_17 P3_18 P3_19 P3_20 P3_21 P3_22 P3_23 P3_24 P3_25 P3_26 P3_27 P3_28 P3_29 P3_30 P3_31 P4_00 P4_01 P4_02 P4_03 P4_04 P4_05 P4_06 P4_07 P4_08 P4_09 P4_10 P4_11 P4_12 P4_25 P4_26 P4_27 P4_28 P4_29 P4_3...

Page 12: ...ace dedicated 16 bit port with special bond out package TEQFP 256 is planned System Control Refer to the platform manual for details Main and sub oscillator is available A wide range of 3 6 16MHz is available for main oscillator 32 kHz is available for sub oscillator Sub clock is enabled disabled by register settings Clock Refer to the platform manual for details CLK_CLKO Clock Output Function is ...

Page 13: ...6 AHB Refer to the platform manual for details MPU for AXI ch 0 Supervise Ethernet MPU for AHB ch 1 Supervise Media LB Additional MPU for graphic subsystem MediaLB and Ethernet AVB These are described in the MPU for AHB and MPU for AXI chapters in the hardware manual To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK Lock 0x112ABB56 Unlock 0xACCABB56 Peripheral Protection Refer to ...

Page 14: ... during the standby mode That is the function is available only for the Backup RAM of 16 KB Resource inter connect The output signal of some resources can be inputted to the other resource I O Ports 5 V GPIO 3 V GPIO Multi input level and multi output drivability Pull up pull down function is available Resource input and output is multiplexed B input is allowed many pins of the 3 3 V 5 V and 3 3 V...

Page 15: ... channels of base timers are available Reload Timer Refer to the platform manual for details I O Timer Refer to the platform manual for details Quad Position Revolution Counter Up Down Counter Refer to the platform manual for details Multi functional Serial MFS Refer to the platform manual for details 5 ports of MFS only support I2 C Note Not all pins support I2 C Only pins which have the I2 C I O...

Page 16: ...e HyperBus Interface Port Configuration of the S6J32E S6J32F S6J32G series hardware manual in detail Stepper Motor Control SMC Each channel has 4 motor drivers with high output capability External Interrupt Capture Unit EICU Refer to the platform manual for details Ethernet AVB 10 100 Mbps MII Interface and RMII Interface Supports audio video bridging AVB See Section 3 2 1 for details MediaLB MOST...

Page 17: ...O Interface Additional Low Latency TX FIFO Interface for DMA configurations MAC Transmit Block half duplex collision back_pressure MAC Filtering Block external address match Wakeup On Lan Energy Efficient Ethernet support LPI Operation in Cadence IP PHY Interface GMII SGMII TBI 10 100 1000 Operation 1000 M SGMII Operation Jumbo Frames Physical Control Sub Layer ...

Page 18: ...MII_REFCLK Not used Used RMII_RX0 Not used Used RMII_RX1 Not used Used RMII_TXD0 Not used Used RMII_TXD1 Not used Used RXD0 Used Not used RXD1 Used Not used RXD2 Used Not used RXD3 Used Not used TXD0 Used Not used TXD1 Used Not used TXD2 Used Not used TXD3 Used Not used RXER Used Not used RXDV Used Used CRS_DV function RXCLK Used Not used TXER Used Not used TXEN Used Used TXCLK Used Not used MDC U...

Page 19: ...ory Reset Factor Operation after Reset is Released Waiting for Stabilization Mode Evaluation Security Evaluation Operation Clock RAM Guarantee Hardware Reset Extended internal power supply low voltage detection reset Flash 1 2 V external power supply control Yes Yes Fast CR No RSTX pin input reset External power supply low voltage detection reset N A Yes Yes Fast CR No ...

Page 20: ...signment drawing specify the I O circuit type described in Section 5 Figure 4 1 Pin Number and I O Circuit Type I O circuit type Pin number Z Z Z Z Z 208 207 206 205 204 203 1 2 A 3 A 4 The following port functions are only supported in certain revisions Port Name Description Package Pin Number Available at revision TEQFP 208 TEQFP 216 TEQFP 256 RXDV Ethernet pin 34 34 34 N ...

Page 21: ...M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCC3 30 127 S AN26 0 AP0 AH0 PWM1P0 OCU6_OTD1 ICU6_IN1 PPG6_TOUT2 EINT5 P3_21 0 DSP0_DATA1_10 0 0 0 0 P5_21 EINT3 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 DSP0_DATA0_4 MDC CAP0_DATA0 0 DSP0_CTRL1 C 31 126 DVCC 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK DSP0_CLK D 3...

Page 22: ...A0 0 DSP0_CTRL1 C 31 132 DVCC 0 0 0 0 0 0 0 0 0 DSP0_DATA0_11 0 0 0 0 0 P0_18 EINT15 PPG3_TOUT2 ICU3_IN1 OCU3_OTD1 0 0 MDIO CAP0_DATA1 DSP0_CLK DSP0_CLK D 32 131 DVSS 0 0 0 0 0 0 0 0 0 DSP0_DATA1_11 0 0 0 0 0 P0_19 EINT0 PPG4_TOUT0 ICU4_IN0 OCU4_OTD0 0 DSP0_DATA1_4 0 CAP0_DATA2 DSP0_CLK DSP0_CTRL2 D 33 130 VSS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P5_27 EINT11 PPG9_TOUT2 ICU9_IN1 OCU9_OTD1 0 TOT0 RXDV CAP...

Page 23: ...N29 0 BN0 BL0 PWM2M0 OCU8_OTD0 ICU8_IN0 PPG8_TOUT0 EINT8 P3_24 0 0 0 0 0 0 0 0 0 P5_28 EINT12 PPG10_TOUT0 ICU10_IN0OCU10_OTD0 0 TIN0 RMII_RXERR CAP0_DATA4 DSP0_DATA_D0 DSP0_DATA1_0 D 35 158 S AN28 0 BP0 BH0 PWM2P0 OCU7_OTD1 ICU7_IN1 PPG7_TOUT2 EINT7 P3_23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSS 36 157 S AN27 0 AN0 AL0 PWM1M0 OCU7_OTD0 ICU7_IN0 PPG7_TOUT0 EINT6 P3_22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 24: ...1 E 0 0 08 4 28 00 BSC 30 00 BSC D 2 A A 1 A 1 35 30 00 BSC 1 40 0 05 SYMBOL MAX 8 0 20 1 45 1 70 0 15 θ D2 D3 E 2 E 3 9 90 REF 8 71 REF 9 90 REF 8 71 REF b 0 17 0 22 0 27 DIMENSION 1 R 0 08 e 0 50 BSC L 2 0 25 D1 D 4 5 7 E1 E 0 20 C A B D 0 10 C A B D D3 D2 E3 E2 A A2 A1 2 11 DETAIL A e 0 08 C SEATING PLANE A A b 0 08 C A B D 8 SIDE VIEW TOPVIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE P...

Page 25: ... BSC 1 70 0 15 0 05 1 35 1 40 1 45 24 00 BSC 9 90 REF 8 70 REF 26 00 BSC 24 00 BSC 9 90 REF 8 70 REF 0 08 0 08 0 20 0 09 0 20 0 13 0 18 0 23 0 45 0 60 0 75 1 00 REF 0 40 BSC D1 D 4 5 7 E1 E 0 20 C A B D 0 10 C A B D D3 D2 E3 E2 A A2 A1 2 11 DETAIL A e 0 08 C SEATING PLANE A A b 0 07 C A B D 8 SIDE VIEW TOPVIEW BOTTOM VIEW b SECTION A A c 10 L1 L θ R1 R2 GAUGE PLANE DETAIL A L2 EXPOSED PAD PACKAGE ...

Page 26: ...Document Number 002 10689 Rev H Page 26 of 166 S6J32E S6J32F S6J32G Series 4 2 3 TEQFP 256 Figure 4 7 LEL 256 002 10752 A ...

Page 27: ...I O circuit type in section 4 1 Type Circuit Remark A Analog output Analog output 3 V Audio DAC output B Analog output Analog output 3 V LVDS output C Pull up control Digital output Digital output Pull down control PSS control TTL input PSS control CMOS hys input General purpose I O port Output 2 mA 5 mA 10 mA or 20 mA selectable 33 kΩ with pull up resistor control 33 kΩ with pull down resistor co...

Page 28: ...ol RSDS output data RSDS output enable Control Logic General purpose I O port Output 2 mA 5 mA 10 mA or 20 mA selectable 33 kΩ with pull up resistor control 33 kΩ with pull down resistor control CMOS hysteresis input TTL input RSDS differential output data E Pull up control Digital output Digital output Pull down control PSS control TTL input PSS control CMOS hys input General purpose I O port Out...

Page 29: ... regulator control Output 2 mA H Pull up control Digital output Digital output Pull down control PSS control Automotive input PSS control CMOS hys input GPIO port Output 1 mA 2 mA or 5 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input I Pull up control Digital output Digital output Pull down control PSS control...

Page 30: ... analog input Output 1 mA 2 mA 3 mA I2 C or 5 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input L CMOS hys input 50 kΩ with pull up CMOS hysteresis input M PSS control OSC input X0 X1 Main oscillation I O N TTL input JTAG_NTRST 50 kΩ with pull down TTL input N2 TTL input JTAG_TDI TMS TCK 50 kΩ with pu...

Page 31: ...OS hys input Analog input GPIO port with analog input Output 1 mA 2 mA 5 mA or 30 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input T Pull up control Digital output Digital output Pull down control PSS control Automotive input PSS control CMOS hys input GPIO port Output 1 mA 2 mA 5 mA or 30 mA selectable 50 kΩ ...

Page 32: ...igital output Pull down control PSS OSC control Automotive input PSS OSC control CMOS hys input Pull up control Digital output Digital output Pull down control PSS OSC control Automotive input PSS OSC control CMOS hys input Sub oscillation I O shared GPIO port Output 1 mA 2 mA or 5 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automot...

Page 33: ...trol Digital output Digital output Pull down control PSS control Automotive input PSS control CMOS hys input TTL input PSS control GPIO port Output 1 mA 2 mA or 5 mA selectable 50 kΩ with pull up resistor control 50 kΩ with pull down resistor control CMOS hysteresis input Automotive hysteresis input TTL input ...

Page 34: ...2 62 64 71 73 80 86 105 116 124 158 172 184 195 1 10 29 42 54 64 66 73 75 82 88 109 120 130 164 180 192 203 1 10 29 36 42 46 52 56 60 64 68 72 79 81 88 90 97 103 129 142 152 194 213 227 240 VSS_LVDS_Tx LVDS Tx GND 15 26 15 26 15 26 AVCC3_DAC Audio DAC power supply pin 6 6 6 Not available on S6J32EE connect to GND AVCC3_LVDS_PLL LVDS PLL power supply pin 13 13 13 AVSS_LVDS_PLL LVDS PLL GND 12 12 12...

Page 35: ...69 TRACE10 Trace data 10 output pin 173 TRACE11 Trace data 11 output pin 177 TRACE12 Trace data 12 output pin 182 TRACE13 Trace data 13 output pin 186 TRACE14 Trace data 14 output pin 197 TRACE15 Trace data 15 output pin 202 TRACE_CLK Trace clock 100 104 124 207 TRACE_CTL Trace control 101 105 125 216 ADTRG A D converter external trigger input pin 118 122 144 AN0 ADC Analog 0 input pin 92 107 AN1 ...

Page 36: ...pin 148 154 183 AN44 ADC Analog 44 input pin 149 155 184 AN45 ADC Analog 45 input pin 150 156 185 AN46 ADC Analog 46 input pin 151 157 187 AN47 ADC Analog 47 input pin 152 158 188 AN48 ADC Analog 48 input pin 153 159 189 AN49 ADC Analog 49 input pin 154 160 190 TX0 CAN transmission data 0 output pin 100 104 124 TX1 CAN transmission data 1 output pin 102 154 106 160 126 190 TX5 CAN transmission dat...

Page 37: ... 201 215 35 63 83 112 165 190 203 238 255 EINT13 External interrupt input pin 36 54 68 93 137 164 174 196 36 56 70 97 143 172 182 204 38 66 85 113 168 204 215 241 EINT14 External interrupt input pin 37 55 67 94 138 165 175 197 37 57 69 98 144 173 183 205 39 67 84 115 170 205 217 243 EINT15 External interrupt input pin 32 38 56 70 95 139 166 176 198 32 38 58 72 99 145 174 184 206 32 40 70 87 116 17...

Page 38: ... Multi function serial ch 1 serial data input pin 84 95 86 99 101 116 SIN2 Multi function serial ch 2 serial data input pin 144 150 178 SIN3 Multi function serial ch 3 serial data input pin 150 156 185 SIN4 Multi function serial ch 4 serial data input pin 154 160 190 SIN8 Multi function serial ch 8 serial data input pin 101 181 105 189 125 224 SIN9 Multi function serial ch 9 serial data input pin ...

Page 39: ...FS17_SDA I2 C ch 17 serial data I O pin 90 93 108 PPG0_TOUT0 Base timer 0 output pin 39 140 161 170 199 39 146 167 178 207 41 172 198 211 245 PPG0_TOUT2 Base timer 1 output pin 40 141 162 169 200 204 40 147 168 177 208 212 44 174 199 210 247 251 PPG1_TOUT0 Base timer 2 output pin 41 142 201 205 41 148 169 209 213 45 175 200 248 252 PPG1_TOUT2 Base timer 3 output pin 143 202 206 44 149 170 210 214 ...

Page 40: ... 167 198 WOT RTC overflow output pin 161 167 198 PWM1M0 SMC ch 0 output pin 128 134 157 PWM1M1 SMC ch 1 output pin 132 138 162 PWM1M2 SMC ch 2 output pin 138 144 170 PWM1M3 SMC ch 3 output pin 142 148 175 PWM1M4 SMC ch 4 output pin 148 154 183 PWM1M5 SMC ch 5 output pin 152 158 188 PWM1P0 SMC ch 0 output pin 127 133 155 PWM1P1 SMC ch 1 output pin 131 137 161 PWM1P2 SMC ch 2 output pin 137 143 168 ...

Page 41: ...tput compare 8 ch 0 output pin 57 78 96 130 189 59 80 100 136 197 71 95 118 159 233 OCU8_OTD1 Output compare 8 ch 1 output pin 58 69 97 131 190 60 71 101 137 198 74 86 119 161 234 OCU9_OTD0 Output compare 9 ch 0 output pin 59 66 98 132 191 61 68 102 138 199 75 83 121 162 235 OCU9_OTD1 Output compare 9 ch 1 output pin 31 34 68 99 133 192 31 34 70 103 139 200 31 34 85 122 163 236 OCU10_OTD0 Output c...

Page 42: ...132 191 61 68 102 138 199 75 83 121 162 235 ICU9_IN1 Input Capture 9 ch 1 input pin 31 34 68 99 133 192 31 34 70 103 139 200 31 34 85 122 163 236 ICU10_IN0 Input Capture 10 ch 0 input pin 35 60 67 100 134 193 35 62 69 104 140 201 35 77 84 124 165 238 ICU10_IN1 Input Capture 10 ch 1 input pin 36 70 101 137 196 36 72 105 143 204 38 87 125 168 241 ICU11_IN0 Input Capture 11 ch 0 input pin 37 63 102 1...

Page 43: ...vailable on S6J32EEx leave open C_R Audio DAC external capacity connection output pin R 4 4 4 DAC_L Audio DAC output pin L 7 7 7 DAC_R Audio DAC output pin R 3 3 3 FRT0 1 2 3_TEXT Free run timer ch 0 1 2 3 clock input pin 160 166 196 FRT4 5 6 7_TEXT Free run timer ch 4 5 6 7 clock input pin 166 174 206 FRT8 9 10 11_TEXT Free run timer ch 4 5 6 7 clock input pin 95 99 116 TIN0 Reload timer ch 0 eve...

Page 44: ...163 52 171 62 203 TOT33 Reload timer ch 33 output pin 54 165 56 173 66 205 TOT34 Reload timer ch 34 output pin 56 167 58 175 70 208 TOT35 Reload timer ch 35 output pin 58 118 60 122 74 144 AIN8 Up Down counter AIN input pin ch 8 190 92 198 107 234 AIN9 Up Down counter AIN input pin ch 9 93 193 97 201 113 238 BIN8 Up Down counter BIN input pin ch 8 90 191 93 199 108 235 BIN9 Up Down counter BIN inp...

Page 45: ... 20 Described as TXOUT4P in FPD Link Converter TxDOUT0 LVDS data output pin 25 25 25 Described as TXOUT0M in FPD Link Converter TxDOUT0 LVDS data output pin 24 24 24 Described as TXOUT0P in FPD Link Converter TxDOUT1 LVDS data output pin 23 23 23 Described as TXOUT1M in FPD Link Converter TxDOUT1 LVDS data output pin 22 22 22 Described as TXOUT1P in FPD Link Converter TxDOUT2 LVDS data output pin ...

Page 46: ...68 70 85 G_DQ2_1 Hyper Bus 1 Data 2 pin 67 69 84 G_DQ3_1 Hyper Bus 1 Data 3 pin 66 68 83 G_DQ4_1 Hyper Bus 1 Data 4 pin 76 78 93 G_DQ5_1 Hyper Bus 1 Data 5 pin 77 79 94 G_DQ6_1 Hyper Bus 1 Data 6 pin 78 80 95 G_DQ7_1 Hyper Bus 1 Data 7 pin 79 81 96 G_RWDS_1 Hyper Bus 1 RWDS pin 699 72 74 89 G_CK_2 Hyper Bus 2 clock output pin 44 46 50 Not available on S6J32EE S6J32FE G_CS 1_2 Hyper Bus 2 select 1 ...

Page 47: ...per Bus Data 3 pin 66 68 83 M_DQ4_0 MCU Hyper Bus Data 4 pin 76 78 93 M_DQ5_0 MCU Hyper Bus Data 5 pin 77 79 94 M_DQ6_0 MCU Hyper Bus Data 6 pin 78 80 95 M_DQ7_0 MCU Hyper Bus Data 7 pin 79 81 96 M_RWDS_0 MCU Hyper Bus RWDS pin 699 72 74 89 DSP0_CLK Display 0 Clock output pin 32 58 32 60 32 74 DSP0_CLK Display 0 RSDS Clock output pin 33 33 33 DSP0_CLK Display 0 RSDS Clock output pin 32 32 32 DSP0_...

Page 48: ... 37 39 DSP0_DATA1_2 Display 0 Data output pin 39 39 41 DSP0_DATA1_3 Display 0 Data output pin 41 41 45 DSP0_DATA1_4 Display 0 Data output pin 33 33 45 33 49 DSP0_DATA1_5 Display 0 Data output pin 45 47 51 DSP0_DATA1_6 Display 0 Data output pin 47 49 55 DSP0_DATA1_7 Display 0 Data output pin 49 51 59 DSP0_DATA1_8 Display 0 Data output pin 51 53 63 DSP0_DATA1_9 Display 0 Data output pin 55 57 67 DSP...

Page 49: ...play 1 Data output pin 201 209 248 DSP1_DATA0_2 Display 1 Data output pin 199 207 245 DSP1_DATA0_3 Display 1 Data output pin 197 205 243 DSP1_DATA0_4 Display 1 Data output pin 193 201 238 DSP1_DATA0_5 Display 1 Data output pin 191 199 235 DSP1_DATA0_6 Display 1 Data output pin 189 197 233 DSP1_DATA0_7 Display 1 Data output pin 187 195 231 DSP1_DATA0_8 Display 1 Data output pin 181 189 224 DSP1_DAT...

Page 50: ...AP0_DATA12 Video Capture 0 Data input pin 45 45 47 49 51 CAP0_DATA13 Video Capture 0 Data input pin 44 46 46 48 50 54 CAP0_DATA14 Video Capture 0 Data input pin 45 47 47 49 51 55 CAP0_DATA15 Video Capture 0 Data input pin 46 48 48 50 54 58 CAP0_DATA16 Video Capture 0 Data input pin 47 49 55 CAP0_DATA17 Video Capture 0 Data input pin 48 50 58 CAP0_DATA18 Video Capture 0 Data input pin 49 51 59 CAP0...

Page 51: ...t 54 56 66 P0_13 GPIO port 55 57 67 P0_14 GPIO port 56 58 70 P0_15 GPIO port 57 59 71 P0_16 GPIO port 58 60 74 P0_17 GPIO port 59 61 75 P0_18 GPIO port 32 32 32 P0_19 GPIO port 33 33 33 P0_26 GPIO port 82 84 99 P0_27 GPIO port 83 85 100 P0_28 GPIO port 84 86 101 P0_30 GPIO port 72 74 89 P0_31 GPIO port 75 77 92 P1_00 GPIO port 77 79 94 P1_01 GPIO port 76 78 93 P1_02 GPIO port 79 81 96 P1_03 GPIO p...

Page 52: ...P3_23 GPIO port 129 135 158 P3_24 GPIO port 130 136 159 P3_25 GPIO port 131 137 161 P3_26 GPIO port 132 138 162 P3_27 GPIO port 133 139 163 P3_28 GPIO port 134 140 165 P3_29 GPIO port 137 143 168 P3_30 GPIO port 138 144 170 P3_31 GPIO port 139 145 171 P4_00 GPIO port 140 146 172 P4_01 GPIO port 141 147 174 P4_02 GPIO port 142 148 175 P4_03 GPIO port 143 149 176 P4_04 GPIO port 144 150 178 P4_05 GP...

Page 53: ...t 202 210 249 P5_20 GPIO port 203 211 250 P5_21 GPIO port 31 31 31 P5_22 GPIO port 60 62 77 P5_27 GPIO port 34 34 34 P5_28 GPIO port 35 35 35 P5_29 GPIO port 36 36 38 P5_30 GPIO port 37 37 39 P5_31 GPIO port 38 38 40 P6_00 GPIO port 39 39 41 P6_01 GPIO port 76 P6_02 GPIO port 111 P6_03 GPIO port 114 P6_04 GPIO port 117 P6_05 GPIO port 120 P6_06 GPIO port 123 P6_07 GPIO port 133 P6_08 GPIO port 138...

Page 54: ...nges for the semiconductor device All the device s electrical characteristics are warranted when operated within these ranges Always use semiconductor devices within the recommended operating conditions Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on t...

Page 55: ...open connections caused by deformed pins or shorting due to solder bridges Use appropriate mounting techniques Cypress recommends the solder reflow method and has established a ranking of mounting conditions for each product Users are advised to mount packages in accordance with Cypress ranking of recommended conditions Pb free Packaging CAUTION When ball grid array BGA packages with Sn Ag Cu ball...

Page 56: ...g 1 Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards If high humidity levels are anticipated consider anti humidity processing 2 Discharge of Static Electricity When high voltage charges exist close to semiconductor devices discharges can cause abnormal operation In such cases use anti static measures or processing to prevent discharges 3 Cor...

Page 57: ...and handle them in the same way as input pins Power Supply Pins If the device has multiple VCC and VSS pins the device is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch up However to reduce unwanted emissions prevent malfunctions of strobe signals caused by an increase of the ground level...

Page 58: ...riving the PSC1 pin low by entering PSS mode power domain 2 off If VCC12 needs to be switched off by other means RSTX needs to be asserted before switching off VCC12 to deactivate the operation of the VCC12 supplied domain below the operation assurance range C Pin Processing This device has a built in voltage step down circuit Be sure to connect a capacitor to the C pin for internal stabilization ...

Page 59: ... shared SMC VI2 VSS 0 3 DVCC 0 3 V 5 V pins shared SMC VI3 VSS 0 3 VCC3 0 3 V 3 V pins VIE VSS 0 3 VCC53 0 3 V 5 V 3 V pins Analog pin input voltage Input voltage for pins shared with ADC 1 VIA1 VSS 0 3 VCC5 0 3 AVCC5 0 3 V 5 V pins not shared SMC VIA2 VSS 0 3 DVCC5 0 3 AVCC5 0 3 V 5 V pins shared SMC Output voltage 1 VO1 VSS 0 3 VCC5 0 3 V 5 V pins not shared SMC 13 VO2 VSS 0 3 DVCC 0 3 V 5 V pin...

Page 60: ...tting is 1 mA 6 7 8 IOHAV2 2 mA When setting is 2 mA 6 7 8 9 IOHAV3 5 mA When setting is 5 mA 6 7 8 9 IOHAV4 10 mA When setting is 10 mA 9 IOHAV5 20 mA When setting is 20 mA 9 IOHAV6 30 mA When setting is 30 mA 7 IOHAV8 6 mA When setting is 6 mA 11 H level total output current 5 ΣIOH1 50 mA 6 10 ΣIOH2 250 mA 7 ΣIOH3 50 mA 8 ΣIOH4 50 mA 9 11 Power dissipation and operation temperature Case 1 PD 330...

Page 61: ... connected to the analog elements It is strongly recommended to set VCC5 DVCC and AVCC5 to the same voltage A Relevant pins All general purpose ports and analog input pins Corresponding pins all general purpose ports Use within the operation assurance condition See 8 2 Operation Assurance Use at DC voltage current The B signal should always be applied by connecting a limiting resistor between the ...

Page 62: ...Series Example of a recommended circuit WARNING Semiconductor devices may be permanently damaged by application of stress including without limitation voltage current or temperature in excess of absolute maximum ratings Do not exceed any of these ratings S6J3200 series ...

Page 63: ... Ripple on FPD Link PLL supply Vpp 7 mV AVCC3_LVDS_PLL peak peak supply noise Smoothing capacitor 1 CS 4 7 µF Tolerance of up to 40 Operating temperature TA 40 105 o C See the notes below TC 40 144 o C Notes 1 For the connections of smoothing capacitor CS see the following diagram Power supply sequence is recommended as VCC5 DVCC or AVCC5 or VCC3 or AVCC3 VCC12 AVCC3_LVDS_PLL or VCC3_LVDS_TX VCC5 ...

Page 64: ...ould be satisfied to facilitate heat dissipation 1 Four or more layers PCB should be used 2 The area of PCB should be 114 3 mm x 76 2 mm or more and the thickness should be 1 6 mm or more JEDEC standard 3 One layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90 or more The layer can be used for system ground 4 35 or more of the die stage a...

Page 65: ...Document Number 002 10689 Rev H Page 65 of 166 S6J32E S6J32F S6J32G Series Figure 8 2 Land Pattern and Thermal via LEQ 216 0 25 mm a 0 30 mm ...

Page 66: ...Document Number 002 10689 Rev H Page 66 of 166 S6J32E S6J32F S6J32G Series Figure 8 3 Land Pattern and Thermal via LET 208 0 25 mm a 0 30 mm ...

Page 67: ...Document Number 002 10689 Rev H Page 67 of 166 S6J32E S6J32F S6J32G Series Figure 8 4 Optional Land Pattern 0 25 mm a 0 30 mm ...

Page 68: ... hysteresis input level is selected 0 7 VCC5 VCC5 0 3 V VIH5 Automotive input level is selected 0 8 VCC5 VCC5 0 3 V VIH6 P2_25 26 P3_00 01 TTL input level is selected 2 0 VCC5 0 3 V VIH7 RSTX NMIX 0 7 VCC5 VCC5 0 3 V VIH8 MD 0 7 VCC5 VCC5 0 3 V VIH9 JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS 2 3 VCC5 0 3 V VIH10 P0_00 to 19 26 to 28 30 31 P1_00 to 09 P5_21 22 27 to 31 P6_00 01 CMOS hysteresis input lev...

Page 69: ... VCC5 V VIL5 Automotive input level is selected VSS 0 3 0 5 VCC5 V VIL6 P2_25 26 P3_00 01 TTL input level is selected VSS 0 3 0 8 V VIL7 RSTX NMIX VSS 0 3 0 3 VCC5 V VIL8 MD VSS 0 3 0 3 VCC5 V VIL9 JTAG_NTRST JTAG_TCK JTAG_TDI JTAG_TMS VSS 0 3 0 8 V VIL10 P0_00 to 19 26 to 28 30 31 P1_00 to 09 P5_21 22 27 to 31 P6_00 01 CMOS hysteresis input level is selected VSS 0 3 0 3 VCC3 V VIL11 P0_00 to 19 3...

Page 70: ...VCC5 0 5 VCC5 V VOH7 PSC_1 VCC5 4 5 V IOH 2 0 mA VCC5 0 5 VCC5 V VOH8 JTAG_TDO VCC5 4 5 V IOH 5 0 mA VCC5 0 5 VCC5 V VOH12 P0_00 to 19 26 to 28 30 31 P1_00 to 09 P5_21 22 27 to 31 P6_00 01 VCC3 3 0 V IOH 2 0 mA VCC3 0 5 VCC3 V VOH13 VCC3 3 0 V IOH 5 0 mA VCC3 0 5 VCC3 V VOH14 VCC3 3 0 V IOH 10 0 mA VCC3 0 5 VCC3 V VOH15 P0_00 to 19 P5_21 22 27 to 31 P6_00 01 VCC3 3 0 V IOH 20 0 mA VCC3 0 5 VCC3 V ...

Page 71: ... 4 V VOL7 PSC_1 VCC5 4 5 V IOL 2 0 mA 0 0 4 V VOL8 JTAG_TDO VCC5 4 5 V IOL 5 0 mA 0 0 4 V VOL9 P2_25 26 P3_00 01 VCC5 4 5 V IOL 3 0 mA 0 0 4 V I2 C VOL12 P0_00 to 19 26 to 28 30 31 P1_00 to 09 P5_21 22 27 to 31 P6_00 01 VCC3 3 0 V IOL 2 0 mA 0 0 4 V VOL13 VCC3 3 0 V IOL 5 0 mA 0 0 4 V VOL14 VCC3 3 0 V IOL 10 0 mA 0 0 4 V VOL15 P0_00 to 19 P5_21 22 27 to 31 P6_00 01 VCC3 3 0 V IOL 20 0 mA 0 0 4 V V...

Page 72: ... to 26 Pull up resistor Selected VCC53 3 0 V to 3 6 V 40 100 200 kΩ 5 V 3 V pins RUP3 P0_00 to 19 26 to 28 30 31 P1_00 to 09 P5_21 22 27 to 31 P6_00 01 Pull up resistor selected 17 33 66 kΩ 3 V pins RUP4 JTAG_TDI JTAG_TMS JTAG_TCK 25 50 100 kΩ Pull down resistor Rdown1 P2_16 17 19 22 24 to 31 P3_00 to 31 P4_00 to 12 P4_25 to 31 P5_00 to 20 P6_02 to 26 Pull down resistor Selected VCC53 4 5 V to 5 5...

Page 73: ...imum deviation of VOL23 90 mV If PWM1P0 PWM1M0 PWM2P0 PWM2M0 of ch 0 is turned on simultaneously the maximum deviation of VOH4 VOL4 for each pin is defined Same for other channels Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Output Differential Voltage VOD DSP0_DATAn DSP0_DATAn n 0 to 11 BOOST 0 Drivability 2 mA RL 100 Ω 100 200 600 mV B...

Page 74: ...ta transfer should be estimated for each port in an actual application and then it should be added to the current consumption at VCC3_LVDS_Tx The current consumption at VCC3_LVDS_Tx is specified under RL 100 ohm CL 5 pF f 50 MHz and 0 1 alternation pattern output 2 This current consumption assumes extremely high activity which is unlikely to achieved in real application Actual current consumption ...

Page 75: ...cillator PD1 ON PD4_0 or PD4_1 ON 445 705 µA 25 CL 10 pF MCGAIN 0b01 8 MHz 8 MHz Crystal for Main Oscillator PD1 ON PD4_0 OFF PD4_1 OFF 440 680 µA 25 CL 10 pF MCGAIN 0b01 8 MHz 32 kHz Crystal for Sub Oscillator PD1 ON PD4_0 ON PD4_1 ON 85 300 µA 25 32 kHz Crystal for Sub Oscillator PD1 ON PD4_0 or PD4_1 ON 80 275 µA 25 32 kHz Crystal for Sub Oscillator PD1 ON PD4_0 OFF PD4_1 OFF 75 250 µA 25 Note ...

Page 76: ...rrent consumption Condition See 8 2 Operation Assurance Symbol Pin Name Conditions Value Unit TA o C Remark Typ Max VCC5 Slow CR oscillator 100 kHz operation mode 1 3 µA 105 Fast CR oscillator 4 MHz operation mode 22 52 µA 105 Before trimming Fast CR oscillator 4 MHz operation mode 17 40 µA 105 After trimming ...

Page 77: ...ernal Slow CR oscillation frequency FCRS 50 100 150 kHz Internal Fast CR oscillation frequency FCRF 2 40 4 00 5 61 MHz Before trim 3 20 4 00 4 81 MHz After trim Notes The maximum minimum values have been standardized with the main clock and PLL clock in use The error of source oscillator frequency must be smaller than 3000 ppm Enough evaluation and adjustment are recommended using oscillator on yo...

Page 78: ...r these clocks are described in Chapter 5 Clock Configuration of the S6J3200 series hardware manual Condition See 8 2 Operation Assurance Table 8 1 Assured Combination of Clock Frequency Symbol Max Value Combination Unit Remarks Max 1 Max 2 Max 3 FSSCG0 232 464 200 800 160 640 MHz SSCG0 output clock FSSCG1 200 800 200 800 200 800 MHz SSCG1 output clock FSSCG2 200 800 200 800 200 800 MHz SSCG2 outp...

Page 79: ...1A0 100 100 100 MHz Unused FCLK_CD1A1 100 100 100 MHz Unused FCLK_CD1B0 100 100 100 MHz Unused FCLK_CD1B1 100 100 100 MHz Unused FCLK_CD2 400 400 400 MHz Unused FCLK_CD2A0 400 400 400 MHz FCLK_CD2A1 400 400 400 MHz Unused FCLK_CD2B0 400 400 400 MHz Unused FCLK_CD2B1 400 400 400 MHz Unused FCLK_CD3 200 200 200 MHz Unused FCLK_CD3A0 200 200 200 MHz FCLK_CD3A1 200 200 200 MHz Unused FCLK_CD3B0 200 20...

Page 80: ...nd 160 MHz of CLK_CPU But each duty ratio of configured 80 MHz as an internal signal is different from one another In this series the 80 MHz from the 160 MHz divided by 2 can only be assured but the 240 MHz divided by 3 cannot be assured from the internal timing design point of view FCLK_TRC 2 half frequency of FCLK_TRC comes out of the trace clock port of package external pin The frequency descri...

Page 81: ...ion Clock Frequency Main Clock PLL Clock Multiplied by 1 Multiplied by 2 Multiplied by 3 Multiplied by 4 Multiplied by 40 Multiplied by 60 Oscillation clock frequency MHz 4 2 4 8 12 16 160 240 Oscillation circuit example Note For the configuration of an oscillation circuit request the oscillator manufacturer to perform a circuit matching evaluation before designing X1 X0 R C2 C1 ...

Page 82: ... input pin Automotive 0 5VCC5 0 8VCC5 Output pin 0 8V 2 4V Hysteresis input pin CMOS Schmitt 0 3VCC5 0 7VCC5 0 3VCC3 0 7VCC3 Hysteresis input pin TTL 0 8V 2 0V DDR HSSPI and HyperBus AC characteristics are specified with the following reference voltages regardless of the automotive input level configuration CMOS Schmitt and TTL Input signal waveform Output signal waveform Input pin Regardless of c...

Page 83: ...arks Min Max Reset input time tRSTL RSTX 10 µs Reset input pulse filter time 1 µs RSTX 0 2VCC 0 2VCC tRSTL 8 4 5 2 Power Supply Voltage Stability Conditions Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max VCC5 stability time after RSTX assertion tFV5 VCC5 35 µs VCC5 2 7 V VCC12 stability time after RSTX assertion tFV12 VCC12 35 µs VCC12 1 1 V ...

Page 84: ...n 0 2 V to 2 65 V 6 mV µs 3 Power ramp rate dV dt VCC5 VCC5 Between 0 2 V to 2 65 V 100 mV µs 4 Maximum ramp rate guaranteed to not generate power on reset dV dt VCC5 VCC5 Between 2 65 V and 4 5 V 50 mV µs 5 Notes 1 If a power fluctuation precedes the low voltage detection time the detection may occur or be canceled after the supply voltage passes the detection voltage range 2 If Vcc is held below...

Page 85: ...tuation is below 50 mV µs the power on reset is suppressed Between 4 5 V to 5 5 V the power on reset does not occur with any VCC5 fluctuation Note When neither 2 nor 3 can be satisfied assert external reset RSTX at power up and at any brownout event Power off time Power ramp rate at Power on VCC tOFF 0 2V 0 2V dV dt Maximum ramp rate guaranteed to not generate power on reset VCC 2 6V dV dt 5 5V dV...

Page 86: ...0_ SPECFGR EX12VRSTCNT 0000 0 7 ms 1 0001 1 4 0010 2 1 0011 2 8 0100 3 5 0101 4 2 0110 4 9 0111 5 7 1000 6 4 1001 7 1 1010 8 5 1011 9 9 1100 11 4 1101 12 8 1110 default 14 2 1111 21 3 VCC12 stabilization time during PSS PD2 off to RUN transition Fast CR trimmed tV12STP2 VCC12 SYSC0_ SPECFGR EX12VRSTCNT 0000 0 8 ms 1 0001 1 6 0010 2 4 0011 3 3 0100 4 1 0101 4 9 0110 5 8 0111 6 6 1000 7 4 1001 8 3 1...

Page 87: ...in Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 CL 50 pF IOL 2 mA IOH 2 mA CL 20 pF IOL 1 mA IOH 1 mA tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns Serial clock H pulse width tSHSL SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR 5 ns Note 1 n 0 ch 0 to ch 4 n 1 ...

Page 88: ...CK1 SCK3 SCK4 SCK8 to SCK12 Master Mode CL 20 pF IOL 5 mA IOH 5 mA 3tCLK_LCPnA 1 ns SCK2 3tCLK_LCP0A SCK16 SCK17 3tCLK_COMP SCK SOT delay time tSLOVI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SOT0 SOT1 SOT3 SOT4 SOT8 to SOT12 2 30 ns 2 20 2 SCK2 SOT2 2 20 SCK16 to SCK17 SOT16 SOT17 2 15 Valid SIN SCK setup time tIVSHI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SIN0 SIN1 SIN3 SIN4 SIN8 to SIN12 26 5 ns 20 2 SCK2 SC...

Page 89: ...5 2 SCK16 SCK17 SOT16 SOT17 0 25 Valid SIN SCK setup time tIVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 SIN17 10 0 ns SCK Valid SIN hold time tSHIXE 1 ns tSCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns Notes 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 2 Group2 of ch 0 ch1 Group1 of ch 8 refer ...

Page 90: ... Page 90 of 166 S6J32E S6J32F S6J32G Series Slave mode tSLSH VIL tSLOVE tIVSHE tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL tF VIH VIL VIH tSHSL tR VIH Master mode tSCYC VOL tSLOVI tIVSHI tSHIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOH ...

Page 91: ... to SCK12 Master Mode CL 20 pF IOL 5 mA IOH 5 mA 3tCLK_LCPnA 1 ns SCK2 3tCLK_LCP0A SCK16 SCK17 3tCLK_COMP SCK SOT delay time tSHOVI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SOT0 SOT1 SOT3 SOT4 SOT8 to SOT12 2 30 ns 2 20 2 SCK2 SOT2 2 20 SCK16 to SCK17 SOT16 SOT17 2 15 Valid SIN SCK setup time tIVSLI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SIN0 SIN1 SIN3 SIN4 SIN8 to SIN12 26 5 ns 20 2 SCK2 SCK16 SCK17 SIN2 SIN...

Page 92: ...25 2 SCK16 SCK17 SOT16 SOT17 0 25 Valid SIN SCK setup time tIVSLE SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 SIN17 10 0 ns SCK Valid SIN hold time tSLIXE 1 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns Notes 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 2 Group2 of ch 0 ch1 Group1 of ch 8 refer ...

Page 93: ... Page 93 of 166 S6J32E S6J32F S6J32G Series Slave mode tSHSL VIL tSHOVE tIVSLE tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL tR VIH VIL VIH tSLSH tF VIL Master mode tSCYC VOH tSHOVI tIVSLI tSLIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOL ...

Page 94: ...SCK SOT delay time tSHOVI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SOT0 SOT1 SOT3 SOT4 SOT8 to SOT12 2 30 ns 2 20 2 SCK2 SOT2 2 20 SCK16 to SCK17 SOT16 SOT17 2 15 Valid SIN SCK setup time tIVSLI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SIN0 SIN1 SIN3 SIN4 SIN8 to SIN12 26 5 ns 20 2 SCK2 SCK16 SCK17 SIN2 SIN16 SIN17 20 SCK Valid SIN hold time tSLIXI SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN...

Page 95: ...SCK setup time tIVSLE SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 SIN17 10 ns SCK Valid SIN hold time tSLIXE 1 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns Notes 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 2 Group2 of ch 0 ch1 Group1 of ch 8 refer to CHAPTER 11 Port Configuration in HWM 3 n 0 ...

Page 96: ... Series Slave mode tSLSH VIL tF tSLIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSLE tSHOVE VIL VIH VIH VIL tSHSL tR Changes when writing to the TDR register Master mode tSCYC VOL tSOVLI tSLIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOH VOH VOL tIVSLI tSHOVI VOL ...

Page 97: ...SCK SOT delay time tSLOVI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SOT0 SOT1 SOT3 SOT4 SOT8 to SOT12 2 30 ns 2 20 2 SCK2 SOT2 2 20 SCK16 to SCK17 SOT16 SOT17 2 15 Valid SIN SCK setup time tIVSHI SCK0 SCK1 SCK3 SCK4 SCK8 to SCK12 SIN0 SIN1 SIN3 SIN4 SIN8 to SIN12 26 5 ns 20 2 SCK2 SCK16 SCK17 SIN2 SIN16 SIN17 20 SCK Valid SIN hold time tSHIXI SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN...

Page 98: ...IVSHE SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 SIN0 to SIN4 SIN8 to SIN12 SIN16 SIN17 10 ns SCK Valid SIN hold time tSHIXE 1 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns SCK rising time tR SCK0 to SCK4 SCK8 to SCK12 SCK16 SCK17 5 ns Notes 1 n 0 ch 0 to ch 4 n 1 ch 8 to ch 12 2 Group2 of ch 0 ch1 Group1 of ch 8 refer to Chapter 11 Port Configuration in the hardware manual 3 n 0 ...

Page 99: ... Series Slave mode tSHSL VIL tR tSHIXE VIH VIL VOH VOL SCK SOT SIN VIH VIL VIH VOH VOL tIVSHE tSLOV E VIL VIH VIH VIL tSLSH tF Changes when writing to the TDR register Master mode tSCYC VOH tSOVHI tSHIXI VIH VIL VOH VOL SCK SOT SIN VIH VIL VOL VOH VOL tIVSHI tSLOVI VOH ...

Page 100: ...marks Min Max SCS SCK setup time tCSSI Master mode CL 20 pF IOL 5 mA IOH 5 mA 20 1 ns SCK SCS hold time tCSHI 3 2 ns SCS deselect time tCSDI 20 5tcp 3 ns SCK SCS clock change time tSCC Round Function Master mode CL 20 pF IOL 5 mA IOH 5 mA 3tcp 0 3tcp 20 ns Notes 1 SCSTR1 CSSU 0 tCSSI can be configured 2 SCSTR0 CSHD 0 tCSHI can be configured 3 SCSTR3 2 CSDS 0 tCSDI can be configured tcp is bus cloc...

Page 101: ...marks Min Max SCS SCK setup time tCSSI Master mode CL 20 pF IOL 5 mA IOH 5 mA 20 1 ns SCK SCS hold time tCSHI 3 2 ns SCS deselect time tCSDI 20 5tcp 3 ns SCK SCS clock change time tSCC Round Function Master mode CL 20 pF IOL 5 mA IOH 5 mA 3tcp 0 3tcp 20 ns Notes 1 SCSTR1 CSSU 0 tCSSI can be configured 2 SCSTR0 CSHD 0 tCSHI can be configured 3 SCSTR3 2 CSDS 0 tCSDI can be configured tcp is bus cloc...

Page 102: ...Document Number 002 10689 Rev H Page 102 of 166 S6J32E S6J32F S6J32G Series ...

Page 103: ...marks Min Max SCS SCK setup time tCSSI Master mode CL 20 pF IOL 5 mA IOH 5 mA 20 1 ns SCK SCS hold time tCSHI 3 2 ns SCS deselect time tCSDI 20 5tcp 3 ns SCK SCS clock change time tSCC Round Function Master mode CL 20 pF IOL 5 mA IOH 5 mA 3tcp 0 3tcp 20 ns Notes 1 SCSTR1 CSSU 0 tCSSI can be configured 2 SCSTR0 CSHD 0 tCSHI can be configured 3 SCSTR3 2 CSDS 0 tCSDI can be configured tcp is bus cloc...

Page 104: ...marks Min Max SCS SCK setup time tCSSI Master mode CL 20 pF IOL 5 mA IOH 5 mA 20 1 ns SCK SCS hold time tCSHI 3 2 ns SCS deselect time tCSDI 20 5tcp 3 ns SCK SCS clock change time tSCC Round Function Master mode CL 20 pF IOL 5 mA IOH 5 mA 3tcp 0 3tcp 20 ns Notes 1 SCSTR1 CSSU 0 tCSSI can be configured 2 SCSTR0 CSHD 0 tCSHI can be configured 3 SCSTR3 2 CSDS 0 tCSDI can be configured tcp is bus cloc...

Page 105: ...Document Number 002 10689 Rev H Page 105 of 166 S6J32E S6J32F S6J32G Series ...

Page 106: ...t Remarks Min Max Serial clock L pulse width tSLSH SCK0 to SCK4 SCK8 to SCK12 CL 50 pF IOL 2 mA IOH 2 mA CL 20 pF IOL 1 mA IOH 1 mA tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns Serial clock H pulse width tSHSL SCK0 to SCK4 SCK8 to SCK12 tCLK_LCPnA 1 10 ns SCK16 to SCK17 tCLK_COMP 10 ns SCK falling time tF SCK0 to SCK4 SCK8 to SCK12 SCK16 to SCK17 5 ns SCK rising time tR 5 ns 1 n 0 ch 0 to ch ...

Page 107: ... start condition setup time SCL SDA tSUSTA SDA4 10 12 16 and 17 SCL4 10 12 16 and 17 4 7 0 6 µs Data hold time SCL SDA tHDDAT SDA4 10 12 16 and 17 SCL4 10 12 16 and 17 0 3 45 1 0 0 9 2 µs Data setup time SDA SCL tSUDAT SDA4 10 12 16 and 17 SCL4 10 12 16 and 17 250 100 ns Stop condition setup time SCL SDA tSUSTO SDA4 10 12 16 and 17 SCL4 10 12 16 and 17 4 0 0 6 µs Bus free time between stop conditi...

Page 108: ...Document Number 002 10689 Rev H Page 108 of 166 S6J32E S6J32F S6J32G Series SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSP tBUF tSUSTO ...

Page 109: ...ns 4tCLK_LCPnA 2 100 ns 100 4tCLK_LCPnA 2 100 ns FRT0_TEXT to FRT11_TEXT 4tCLK_LCPnA 2 ns 4tCLK_LCPnA 2 100 ns 100 4tCLK_LCPnA 2 100 ns TIN0 to TIN3 TIN16 to TIN19 4tCLK_LCPnA 3 ns 4tCLK_LCPnA 3 100 ns 100 4tCLK_LCPnA 3 100 ns TIN32 to TIN35 4tCLK_LLPBM2 ns 4tCLK_LLPBM2 100 ns 100 4tCLK_LLPBM2 100 ns TIN48 to TIN49 4tCLK_COMP ns 4tCLK_COMP 100 ns 100 4tCLK_COMP 100 ns Notes 1 n 0 ch 0 to ch 5 n 1 ...

Page 110: ...2E S6J32F S6J32G Series 8 4 9 Trigger Input Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH tTRGL EINT0 to EINT15 100 ns Trigger input timing VIH VIL EINTx tTRGL tTRGH VIH VIL ...

Page 111: ...it Remarks Min Typ Max Detection Voltage 0 9 0 95 1 0 V 1 Release Voltage 0 925 1 025 1 125 V Level Detection Time 30 s 2 Notes 1 This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage as these detection levels are below the minimum guaranteed MCU operation voltage 2 After the brown out event where the voltage level dips below the de...

Page 112: ...tage 0 945 1 045 1 145 V Detection Voltage LVDL1V 11 1 02 1 07 1 12 V Release Voltage 1 095 1 145 1 195 V Detection Time 30 μs 2 Notes 1 This LVD cannot be used to reliably generate a reset before voltage dips below the minimum guaranteed MCU operation voltage as these detection levels are below the minimum guaranteed MCU operation voltage 2 After the brown out event where the voltage level dips b...

Page 113: ...VCC5 LVDH1V 0101 3 80 4 00 4 20 V Release Voltage VCC5 3 90 4 10 4 30 V Detection Voltage VCC5 LVDH1V 0110 Default 4 00 4 20 4 40 V Release Voltage VCC5 4 10 4 30 4 50 V Detection Voltage VCC5 LVDH1V 0111 4 20 4 40 4 60 V Release Voltage VCC5 4 30 4 50 4 70 V Detection Voltage VCC5 LVDH1V Other 4 40 4 65 4 90 V Release Voltage VCC5 4 50 4 75 5 00 V Detection Time 30 μs 2 Power supply voltage regul...

Page 114: ...FV5 VCC5 55 µs VCC5 2 7 V VCC12 stability time after LVDH1 low voltage detection tFV12 VCC12 55 µs VCC12 1 1 V LVDH1 detect voltage tFV12 1 1V 2 7V tFV5 VCC12 PSC_1 VCC5 The behavior of PSC_1 depends on EXVRSTCNT bit If the bit is set to 1 PSC_1 keeps H level 8 4 11 5 LVDL2 Condition See 8 2 Operation Assurance Parameter Pin Name Conditions Value Unit Guaranteed MCU operation range Remarks Min Typ...

Page 115: ...0 92 0 97 1 02 V Release Voltage VCC12 0 995 1 045 1 095 V Detection Voltage VCC12 LVDL2V 11 1 02 1 07 1 12 V Release Voltage VCC12 1 095 1 145 1 195 V Detection Time 30 μs 2 Notes 1 This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage as these detection levels are below the minimum guaranteed MCU operation voltage 1 1 V 2 After th...

Page 116: ...C3 LVDH2V 0010 2 7 2 85 3 0 V Yes Release Voltage VCC3 2 8 2 95 3 1 V Detection Time 30 μs 2 Power supply voltage regulation VCC5 2 2 V ms 3 Notes 1 These LVD settings cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage as these detection levels are below the minimum guaranteed MCU operation voltage 2 7 V 2 After the brown out event where ...

Page 117: ...2E S6J32F S6J32G Series 8 4 12 High Current Output Slew Rate Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Output rise fall time tR2 tF2 P3_21 to 31 P4_00 to 12 15 100 ns Load capacitance 85 pF ...

Page 118: ...CC3 domain DSP0_CLK to Data Control valid time tDC0H 0 5 ns Data Control output to DSP0_CLK time tDC0S DSP0_CTRL11 0 CL 20 pF IOL 5 mA IOH 5 mA tDCOCYC 9 3 ns If any of DSP0_CTRL11 0 in VCC53 domain is used DSP0_CLK to Data Control valid time tDC0H 1 ns Notes For 1 when used with DSP0_DATA and DSP0_CTRL4 0 in the VCC3 area For 2 when used with DSP0_CTRL11 0 in the VCC53 area Values valid for unshi...

Page 119: ...P0_CLK CL 20 pF IOL 4 mA IOH 4 mA 15 625 ns Data output to DSP0_CLK time tRSS DSP0_DATA_D11 0 DSP0_DATA_D11 0 tRSCYC 2 5 7 ns DSP0_CLK to Data valid time tRSH 0 1 ns Control output to DSP0_CLK time tSPS DSP0_CTRL11 0 tRSCYC 9 5 ns DSP0_CLK to Control valid time tSPH 0 4 ns Note The clock output delay can be adjusted See the Graphic Subsystem chapter in the TRM for details Values valid for unshifte...

Page 120: ...20 pF IOL 5 mA IOH 5 mA 20 0 ns Data Control output to DSP1_CLK time tDC1S DSP1_DATA0_11 0 DSP1_DATA1_11 0 DSP1_CTRL2 0 tDC1CYC 4 6 ns DSP1_CLK to Data Control valid time tDC1H 6 ns Notes The clock output delay can be adjusted See the Graphic Subsystem chapter in the TRM for details Values valid for unshifted display clock dsp_ClockInvert 0 dsp_ClockShift 0 tDC1CYC DSP1_CLK VOH VOH valid tDC1S tDC...

Page 121: ...ming Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Clock Cycle tCAP0CYC CAP0_CLK 12 5 ns Capture data setup time tCAP0SU CAP0_DATA35 0 4 0 ns Capture data hold time tCAP0HD CAP0_DATA35 0 1 0 ns tCAP0CYC CAP0_CLK VIH VIH VIH valid tCAP0SU tCAP0HD CAP0_DATA35 0 VIH VIL ...

Page 122: ... 235 0 0 235 ns Output pulse position for bit 1 T1 1 7 x T 0 235 1 7 x T 1 7 x T 0 235 ns Output pulse position for bit 2 T2 2 7 x T 0 235 2 7 x T 2 7 x T 0 235 ns Output pulse position for bit 3 T3 3 7 x T 0 235 3 7 x T 3 7 x T 0 235 ns Output pulse position for bit 4 T4 4 7 x T 0 235 4 7 x T 4 7 x T 0 235 ns Output pulse position for bit 5 T5 5 7 x T 0 235 5 7 x T 5 7 x T 0 235 ns Output pulse p...

Page 123: ...6 7 x T 0 45 ns Output pulse position for bit 0 T0 f 5 MHz 2 00 0 2 00 ns Output pulse position for bit 1 T1 1 7 x T 2 00 1 7 x T 1 7 x T 2 00 ns Output pulse position for bit 2 T2 2 7 x T 2 00 2 7 x T 2 7 x T 2 00 ns Output pulse position for bit 3 T3 3 7 x T 2 00 3 7 x T 3 7 x T 2 00 ns Output pulse position for bit 4 T4 4 7 x T 2 00 4 7 x T 4 7 x T 2 00 ns Output pulse position for bit 5 T5 5 7...

Page 124: ...Series Figure 8 5 LVDS AC Timing Chart D1 D0 D6 D5 D4 D3 D2 D1 D2 D3 D0 D6 TxDOUT3 TxCLK D1 D0 D6 D5 D4 D3 D2 D1 D2 D3 D0 D6 TxDOUT2 D1 D0 D6 D5 D4 D3 D2 D1 D2 D3 D0 D6 TxDOUT1 D1 D0 D6 D5 D4 D3 D2 D1 D2 D3 D0 D6 TxDOUT0 TCIP TH TL T0 T1 T2 T3 T4 T5 T6 TCSK TCDT TH TH TL ...

Page 125: ...89 Rev H Page 125 of 166 S6J32E S6J32F S6J32G Series Figure 8 6 LVDS AC Timing Chart Tx M Tx P Delta VCM 0 Voltage V VCM VOD Delta VOD VOD max VOD min Single End Tx M Tx P 0 Voltage V VCM TDSK Common voltage for each data bit ...

Page 126: ...ing Quad Page mode or Dual Quad mode GSDATA G_SCLK Input setup time tisdata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 1 ns G_SCLK GSDATA Input hold time tihdata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 1 ns G_SCLK GSDATA Output delay time toddata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 tcyc 2 1 5 ns G_SCLK GSDATA Output hold time tohdata G_SDATA0_0 3 G_SDATA1_0 3 M...

Page 127: ...32G Series tcyc VIH VIL G_SCLK 0 G_SDATA0_0 3 G_SDATA1_0 3 inputtiming VOH VOH VIH VIL valid tisdata Delayed sample clock tihdata V OH tspcnt VOH VOL G_SDATA 0_0 3 G_SDATA 1_0 3 output timing V OH VOL valid toddata tohdata V OL GSSEL0 1 outputtiming VOH todsel tohsel ...

Page 128: ...ATA Input hold time tihdata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 1 ns G_SCLK GSDATA Output delay time toddata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 tcyc 4 0 9 ns G_SCLK GSDATA Output hold time tohdata G_SDATA0_0 3 G_SDATA1_0 3 M_SDATA0_0 3 M_SDATA1_0 3 Tcyc 4 1 55 ns GSSEL G_SCLK Output delay time todsel G_SSEL0 1 M_SSEL0 1 SS2CD 0 75 tcyc 3 375 ns G_SCLK GSSEL Output ...

Page 129: ...Document Number 002 10689 Rev H Page 129 of 166 S6J32E S6J32F S6J32G Series ...

Page 130: ... and TTL 8 4 17 1 HyperBus Write Timing HyperFlash Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max HyperBus clock cycle tCKCYC G_CK M_CK CL 20 pF IOL 10 mA IOH 10 mA 10 ns CS CK Chip Select setup time tCSS G_CS _1 2 M_CS _1 2 tCKCYC 2 0 ns DQ CK Setup time tIS G_DQ7 0 M_DQ7 0 1 25 ns CK DQ Hold time tIH G_DQ7 0 M_DQ7 0 1 25 ns CK CS Chip select...

Page 131: ... Select setup time tCSS G_CS _1 2 M_CS _1 2 tCKCYC 2 0 ns DQ CK Setup time tIS G_DQ7 0 M_DQ7 0 1 25 ns CK DQ Hold time tIH G_DQ7 0 M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH G_CS _1 2 M_CS _1 2 tCKCYC 2 ns RWDS CK Data Mask Valid tDMV G_RWDS M_RWDS 1 ns CK RWDS Refresh Indicator Valid tRIV G_RWDS M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH G_RWDS M_RWDS 0 ns Note HyperBus clock cycl...

Page 132: ... cycle tRDSCYC G_CK G_RWDS M_CK M_RWDS CL 20 pF IOL 10 mA IOH 10 mA 10 ns CS CK Chip Select setup time tCSS G_CS _1 2 M_CS _1 2 tRDSCYC 2 0 ns DQ CK Setup time tIS G_DQ7 0 M_DQ7 0 1 25 ns CK DQ Hold time tIH G_DQ7 0 M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH G_CS _1 2 M_CS _1 2 tRDSCYC 2 ns DQ RDS Setup time tDSS G_DQ7 0 M_DQ7 0 0 9 ns RDS DQ Hold time tDSH G_DQ7 0 M_DQ7 0 1 0 ns Note HyperB...

Page 133: ..._CS _1 2 M_CS _1 2 tRDSCYC 2 0 ns DQ CK Setup time tIS G_DQ7 0 M_DQ7 0 1 25 ns CK DQ Hold time tIH G_DQ7 0 M_DQ7 0 1 25 ns CK CS Chip select hold time tCSH G_CS _1 2 M_CS _1 2 tRDSCYC 2 ns DQ valid RWDS Setup time tDSS G_DQ7 0 M_DQ7 0 0 9 ns RWDS DQ invalid Hold time tDSH G_DQ7 0 M_DQ7 0 1 0 ns CK RWDS Refresh Indicator Valid tRIV G_RWDS M_RWDS 6 ns CK RWDS Hi z Refresh Indicator Hold tRIH G_RWDS ...

Page 134: ...etup time tRXS RXER RXDV RXD0 3 10 0 ns tRXCYC 30 ns RX hold time tRXH RXER RXDV RXD0 3 2 ns tRXCYC RXCLK VIH VIH valid VIH VIL tRXS tRXH RXER RXDV RXD0 3 8 4 18 2 Ethernet Transmit Timing MII Interface Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max TXCLK cycle tTXCYC RXCLK CL 20 pF IOL 5 mA IOH 5 mA 40 0 ns Tx delay time tTXD TXER TXEN TXD0 3...

Page 135: ...ter Symbol Pin Name Conditions Value Unit Remarks Min Max MDC cycle tMDCYC MDC CL 20 pF IOL 5 mA IOH 5 mA 400 0 ns MDIO input setup time tMDIS MDIO 100 0 ns MDIO input hold time tMDIH MDIO 0 0 ns MDIO output delay time tMDOD MDIO 10 0 390 0 ns tMDCYC MDC VOH VOH VOH VOL valid VIH VIL tMDIS tMDIH MDIO in valid VOH VOL tMDOD tMDOD MDIO out VOH ...

Page 136: ...lue Unit Remarks Min Max Reference clock cycle tREFCLK RMII_REFCLK 20 ns Reference clock duty cycle tREFDTY 35 65 Data setup to RMII_REFCLK rising edge tSU RMII_RXD 1 0 RMII_RXERR RXDV 1 4 ns Data hold from RMII_REFCLK rising edge tHOLD 2 ns Data output delay from RMII_REFCLK rising edge tTXOUT RMII_TXD 1 0 TXEN CL 25 pF IOL 10 mA IOH 10 mA 2 13 ns Note 1 RXDV pin is used for CRS_DV function of RM...

Page 137: ...1B0 internal frequency MLBCLK external frequency 8 4 19 2 MediaLB Output Timing Condition See 8 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MLBCLK cycle tmckc MLBCLK CL 20 pF IOL 6 mA IOH 6 mA 39 ns MLBSIG MLBDAT output stop tmcfdz MLBSIG MLBDAT 26 5 ns tmckc tdout MLBSIG MLBDAT output delay tdout MLBSIG MLBDAT 0 12 5 ns Notes CLK_HAPP1B0 internal frequenc...

Page 138: ...CP1A ns Rising timing of AIN from L level of BIN tBDAU AIN PC_Mode2 or PC_Mode3 4tCLK_LCP1A ns Rising timing of AIN from H level of BIN tBUAU AIN PC_Mode2 or PC_Mode3 4tCLK_LCP1A ns Falling timing of BIN from H level of AIN tAUBD BIN PC_Mode2 or PC_Mode3 4tCLK_LCP1A ns Falling timing of AIN from L level of BIN tBDAD AIN PC_Mode2 or PC_Mode3 4tCLK_LCP1A ns Rising timing of BIN from L level of AIN t...

Page 139: ...Document Number 002 10689 Rev H Page 139 of 166 S6J32E S6J32F S6J32G Series tZLL ZIN tZHL ｔBHL AIN tBLL tBUAU tAUBD tALL tAHL tADBU BIN tBDAD tAHL BIN tALL tAUBU tBUAD tBLL tBHL tBDAU AIN tADBD ...

Page 140: ...Document Number 002 10689 Rev H Page 140 of 166 S6J32E S6J32F S6J32G Series tABEZ ZIN tZABE AIN BIN ...

Page 141: ... 2 Operation Assurance Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse filter time All GPIOs 67 ns EINT0 15 TIN0 3 16 19 32 35 48 49 67 ns ADTRG 67 ns SCL4 10 12 16 17 SDA4 10 12 16 17 240 ns Note The spec guarantees that a rectangular pulse wider than the max filter time is never removed ...

Page 142: ...bol Pin Name Conditions Value Unit Remarks Min Max TMS TDI setup time tJTAGS JTAG_TCK JTAG_TMS JTAG_TDI CL 20 pF 16 ns TMS TDI hold time TJTAGH JTAG_TCK JTAG_TMS JTAG_TDI 10 ns TDO delay time TJTAGD JTAG_TCK JTAG_TDO 25 ns VOL VOH ＶＯＨＭＣＳＸ０７ｔＣＳＷＶＯＬＳＲＡＭリード JTAG_TCK JTAG_TMS JTAG_TDI tJTAGD JTAG_TDO VIL VIH VIL VIH tJTAGS VIL VIH tJTAGH ...

Page 143: ...0 35 tsck 0 65 tsck ns I2S clock L pulse width tslw 0 35 tsck 0 65 tsck ns Sender delay time SCK SD WS valid tdtr I2S0_SCK I2S1_SCK I2S0_SD I2S1_SD I2S0_WS I2S1_WS 35 ns 2 Sender hold time SCK SD WS invalid thtr 10 ns 2 Receiver setup time SD valid SCK tsr I2S0_SCK I2S1_SCK I2S0_SD I2S1_SD 40 ns 2 Receiver hold time SCK SD valid thr 10 ns 2 Notes 1 ECKM 1 Refer to the Resource Input Configuration ...

Page 144: ... pulse width tslw 0 40 tsck 0 60 tsck ns Setup time WS transition SCK tsrf I2S0_SCK I2S1_SCK I2S0_WS I2S1_WS 40 ns 1 Hold time SCK WS transition thrf 10 ns 1 Sender delay time SCK SD valid tdtr I2S0_SCK I2S1_SCK I2S0_SD I2S1_SD 35 ns 1 Sender hold time SCK SD invalid thtr 10 ns 1 Receiver setup time SD valid SCK tsr I2S0_SCK I2S1_SCK I2S0_SD I2S1_SD 40 ns 1 Receiver hold time SCK SD valid thr 10 n...

Page 145: ...tion Assurance Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution 12 bit Total Error 12 LSb 3 Integral Non linearity 4 0 LSb 4 Differential Non linearity 1 9 LSb 4 Zero transition voltage VZT AN0 to AN49 AVRL 11 5LSb AVRL 12 5LSb V 5 Full scale transition voltage VFST AN0 to AN49 AVRH 13 5LSb AVRH 10 5LSb V Sampling time tSMP 0 3 µs 1 Compare time tCMP 0 8 28 µs 1 A D conversion t...

Page 146: ...ce voltage AVRH AVRH5 4 5 5 5 V AVCC AVRH AVRL AVRL5 AVSS 0 0 V Power supply current IA AVCC 500 900 µA IAH 1 0 100 µA 2 IR AVRH 1 0 2 0 mA IRH 5 0 µA 2 Variation between channels AN0 to AN49 4 0 LSb Notes 1 Time per channel 2 Definition of the power supply current when VCC AVCC 5 0 V while the A D converter is not operating and in stop mode 3 Total Error is a comprehensive static error that inclu...

Page 147: ... the straight line connecting the zero transition point 0000 0000 0000 0000 0000 0001 and full scale transition point 1111 1111 1110 1111 1111 1111 from actual conversion characteristics includes zero transition error full scale transition error and non linearity error Differential linearity error Deviation from the ideal value of the input voltage required for changing the output code by 1 LSb To...

Page 148: ...converter digital output value VZT Ideal value AVRL 0 5LSb V VFST Ideal value AVRH 1 5LSb V VNT Voltage at which the digital output changes from N 1 to N FFF FFE FFD 004 003 002 001 AVRL AVSS AVRH 1 LSb N 1 0 5LSb 1 5LSb VNT 0 5LSb Ideal characteristics Actual conversion characteristics Actually measured value Analog input Actual con ver sion cha ract eris tics measured value Digital output ...

Page 149: ...tal output changes from 0x000 to 0x001 VFST Voltage for which digital output changes from 0xFFE to 0xFFF FFF FFE FFD 004 003 002 001 AVSS AVRL AVRH AVRH Actual conversion characteristics 1 LSb N 1 VZT N 1 AVSS AVRL N 2 N N 1 VFST VNT VZT V N 1 T VNT Ideal characteristics Actual conversion characteristics Actual conversion characteristics Actual conversion characteristics Ideal characteristics Digi...

Page 150: ...equency 1 kHz LPF fc 20 kHz 82 72 dB SNR 3 Signal frequency 1 kHz LPF fc 20 kHz A weighting filter 85 89 dB Dynamic range 3 83 86 dB Out of Band Energy 20 kHz to 64fs 33 dB Channel Separation 80 dB Output impedance 150 200 250 Ω PSRR Digital input zero noise 50 Hz 35 dB noise 1 kHz 50 dB noise 20 kHz 40 dB Digital input full scale sine 13 dB Supply current normal operation AVCC3 _DAC 2 2 3 2 mA Su...

Page 151: ...nce α Capacitance variance 3 Startup time Start up time typ 1 α ms For example CCOM 11 µF then α 11 µF 10 µF 10 µF 10 So Startup time 650 ms 1 10 100 715 ms Notes Two uses of RL load connection Case1 RL is connected to AVCC3_DAC 2 Figure 8 8 Case2 The coupling capacitance must be inserted as shown in Figure 8 9 Figure 8 8 RL is Connected to AVCC_DAC 2 Example CL max 100pF DAC_L DAC_R RL min 20kΩ A...

Page 152: ...e Regulator DAC_R DAC_L Post LPF Buffer Post LPF Buffer C5 C6 Notes C1 more than 10 μF low ESR capacitors C2 0 1 μF ceramic capacitors C3 C4 C5 C6 10 μF low ESR capacitors Impedance of each power line must be as low as possible Notes When DAC is not used in your system the related pins should be AVCC3_DAC GND and AVSS GND C_L OPEN and C_R OPEN DAC_L OPEN and DAC_R OPEN ...

Page 153: ...s System level overhead time excluded 1 32bit with ECC write time 31 651 µs System level overhead time excluded 1 64bit with ECC write time 49 1029 µs System level overhead time excluded 1 Erase count 2 Data retention time 1 000 20 years 10 000 10 years 100 000 5 years Temperature at write erase time Average temperature TA 85 C Notes 1 Guaranteed value for up to 100 000 erases 2 Number of erases f...

Page 154: ...Cyclic Redundancy Check CSV Clock SuperVisor DAC Digital Analog Converter DAP Debug Access Port DED Dual Error Detection DMA Direct Memory Access DMAC DMA Controller EAM Exclusive Access Memory ECC Error Correction Code ETM Embedded Trace Macro EXT IRC External InteRrupt Controller FIQ Fast Interrupt Request FPU Floating Point Unit FRT Free Run Timer GPIO General Purpose I O HPM High Performance M...

Page 155: ...duced Swing Differential Signal RTC Real Time Clock RVD Low Voltage Detection and Reset for RAM Retention SCT Source Clock Timer SEC Single Error Correction SECDED Single Error Correction and Dual Error Detection SHE Secure Hardware Extension SMC Stepper Motor Controller SMIX Sound Mixer SPI Serial Peripheral Interface SRAM Static RAM SSCG Spread Spectrum Clock Generation SWFG Sound Waveform Gener...

Page 156: ... S6J32E S6J32F S6J32G Series 10 Ordering Information Table 10 1 Order Part Number Table Part Number Package S6J32GEKSMSE2000A LET208 208 pin plastic TEQFP S6J32GEKSNSE20000 LET208 208 pin plastic TEQFP S6J32EELTMSC2000A LEQ216 216 pin plastic TEQFP ...

Page 157: ... note AN209861 Getting Started with the Traveo Family S6J3200 Series for details DGND S6J3200 JTAG ARM 20pin 5V0_S R 5V0_S R 112 114 116 115 113 118 JTAG_NTRST JTAG_TDI JTAG_TMS JTAG_TCK R 20ohm JTAG_TDO RSTX DGND DGND R R 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Vsense GND GND nTRST TDI TMS TCK RTCK TDO nRESET Pull down Pull down VCC GND GND GND GND GND GND GND 5V0_S R R R R R R 216pin ...

Page 158: ... LVDS power supply Section 8 4 2 2 removed drawing for LER 208 Section 8 4 4 changed AC timing Section 8 4 12 2 updated AC spec Section 8 4 6 2 CSIO timing updated to actual design Section 8 4 15 2 Updated DDRHSSPI AC timing SDR added Dual Quad mode for 50 MHz DDR added 40 MHz limitation for Quad mode and Dual quad mode Removed RXx from list of trigger inputs DDRHSSPI AC timing added falling edge ...

Page 159: ...ing of Analog pin input voltage Section 8 2 Deleted Supply stabilization time more detailed spec already added in 8 4 5 Section 8 3 1 VIH13 14 refers to DVcc not Vcc5 VOL4 5 6 corrected list of applicable pins Deleted footnote 1 about pins supplied with DVcc Information is included in table IIL RUP2 RDOWN1 corrected list of applicable pins removed not existing pins Section 8 3 2 2 and 8 3 2 3 Dele...

Page 160: ... 3 2 Added comment to CAN FD spec CAN FD rev 3 2 is used Section 8 4 10 6 corrected typical release voltage for setting 0001 from 2 75 V to 2 85 V Section 2 2 1 deleted two notes about devices w o FPD link Section 3 2 added initial main clock stabilization time in table 3 1 Section 8 4 6 4 changed name High speed mode to Fast mode Section 3 2 added Interrupt Enable Register in table 3 1 for HyperB...

Page 161: ...on 8 4 12 1 2 Display controller DSP0 change max frequency from 80 MHz to 64 MHz to match guaranteed performance of Graphic subsystem Section 8 4 6 3 MFS CSIO changed tSOVLI and tSOVHI to 2x tclk Section 8 4 6 2 1 4 removed redundant information from tSCYC tSHSL tSLSH 1 2 removed obsolete footnote 2 and changed footnote number 3 to 2 3 4 flipped footnote 2 3 and updated footnote assignment at tSOV...

Page 162: ...A0 from VCC53 Section 8 4 5 Reset added subsection for supply stability conditions Section 8 4 5 2 added symbol for VCC12 stabilization time Section 8 4 6 1 added voltage ramp 100mV us Section 8 4 7 2 CSIO Timing Add LIN Tslove min parameter Section 8 4 7 2 CSIO Timing Updated tSLOVE tSHOVE tIVSLE tIVSHE Section 8 4 7 2 CSIO Timing revised tSLOVE tSHOVE tIVDLE tIVSHE Section 8 4 7 2 CSIO Timing co...

Page 163: ...or supply stability by references to section 8 4 5 and 8 4 11 4 Section 8 4 4 8 8 4 16 specified DDR HSSPI AC characteristics reference voltage of VIL VIH VOL VOH 0 5 Vcc3 Section 8 2 23 I2S added AC characteristics Removed status advance F 5727929 ANMA 05 08 2017 Section 8 3 2 2 Section 8 3 2 3 Power supply current Removed note The values will be evaluated after engineering samples release becaus...

Page 164: ...re is no footnote 3 G 5917755 ANMA 10 12 2017 Section 2 2 2 ID Added new table for IDs for and changed Chip IDs and JTAG IDs for S6J32xxxxN Section 6 1 Port description removed CRS pin because it s only required for Ethernet Half duplex mode which is not supported Section 6 1 Port description Added alternative pin 34 for RXDV except for revision M Section 3 2 1 Ethernet removed CRS and COL pin fro...

Page 165: ...hared Section 8 2 allowed additional two power sequences Same as in S6J3200 Datasheet Section 5 1 I O Circuit type Type E 3V IO corrected pull up down from 50kOhm to 33 kOhm H 5991338 ANMA 12 12 2017 Section 10 Ordering information corrected part number S6J32GEKSMSC2000A S6J32GEKSMSE2000A S6J32GEKSNSC20000 S6J32GEKSNSE20000 Corrected package code for TEQFP 208 from LEQ208 to LET208 Whole document ...

Page 166: ...are infringed by the Software as provided by Cypress unmodified to make use distribute and import the Software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence Any other use reproduction modification translation or compilation of the Software is prohibited CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMP...

Page 167: ...miconductor S6J32GEKSMSE20000 S6J32GEKUMSE20000 S6J32GELTMSC20000 S6J32GELSMSC20000 S6J32GEKSMSE2000A S6J32EELTMSC20000 S6J32EELTMSC2000A S6J32EEKSNSE20000 S6J32EELSNSC20000 S6J32EELTPSC20000 S6J32FEKSNSE20000 S6J32FELSNSC20000 S6J32GEKSNSE20000 S6J32GELSNSC20000 S6J32GELTPSC20000 S6J32GELTNSC20000 S6J32FELTNSC20000 ...

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