Document Number: 002-10689 Rev *H
Page 143 of 166
S6J32E, S6J32F, S6J32G Series
8.4.23
I2S
8.4.23.1
I2S Timing
– Master mode (MSMD=1)
Parameter
Symbol
Pin Name
Conditions
Value
Uni
t
Remarks
Min
Max
ECLK0/ECLK1 clock
cycle
t
eck
ECLK0,
ECLK1
(CL = 20 pF,
I
OL
= -5 mA,
I
OH
= 5 mA)
CPOL = 0,
SMPL = 1
20
-
ns
Only relevant if
external ECLK input is
selected.
*1
ECLK0/ECLK1 clock
“H” pulse width
t
ehw
0.40*
t
eck
0.60*
t
eck
ns
ECLK0/ECLK1 clock
“L” pulse width
t
elw
0.40*
t
eck
0.60*
t
eck
ns
I2S clock cycle
(output SCK)
t
sck
I2S0_SCK,
I2S1_SCK
66.66
-
ns
I2S clock “H” pulse
width
t
shw
0.35*
t
sck
0.65*
t
sck
ns
I2S clock “L” pulse
width
t
slw
0.35*
t
sck
0.65*
t
sck
ns
Sender delay time
SCK↑ -> SD/WS
valid
t
dtr
I2S0_SCK,
I2S1_SCK,
I2S0_SD,
I2S1_SD,
I2S0_WS,
I2S1_WS
-
35
ns
*2
Sender hold time
SCK↑ -> SD/WS
invalid
t
htr
-10
-
ns
*2
Receiver setup time
SD valid -
> SCK↑
t
sr
I2S0_SCK,
I2S1_SCK,
I2S0_SD,
I2S1_SD
40
-
ns
*2
Receiver hold time
SCK↑ -> SD valid
t
hr
10
-
ns
*2
Notes:
*1: ECKM = 1. Refer to the Resource Input Configuration chapter in
for required RESSEL register settings.
*2: Refer to the I2S register description chapter in the
for different combinations of clock polarity (CPOL), sampling point
position (SMPL), polarity/pulse_width/frame_sync phase of WS (FSPL, FSLN, FSPH). Actual waveforms and relevant clock
edges will change accordingly; the delay values based on the table above will remain the same.
