![Compaq AlphaServer ES40 Service Manual Download Page 380](http://html.mh-extra.com/html/compaq/alphaserver-es40/alphaserver-es40_service-manual_2645524380.webp)
D-22
Compaq AlphaServer ES40 Service Guide
Table D–8 I_CTL Register Fields (Continued)
Name
Extent
Type
Description
SPE[2:0]
[5:3]
RW,0
Super Page Mode Enable.
Identical to the SPE bits in the Mbox
M_CTL SPE[2:0].
IC_EN[1:0]
[2:1]
RW,3
Icache Set Enable.
At least one set must be enabled. The entire
cache may be enabled by setting both bits.
Zero, one, or two Icache sets can be enabled.
This bit does not clear the Icache, but only
disables fills to the affected set.
SPCE
[0]
RW,0
System Performance Counting Enable.
Enables performance counting for the entire
system if individual counters (PCTR0 or
PCTR1) are enabled by setting PCT0_EN or
PCT1_EN, respectively.
Performance counting for individual
processes can be enabled by setting
PCTX[PPCE].
Summary of Contents for AlphaServer ES40
Page 4: ......
Page 16: ......
Page 20: ......
Page 68: ......
Page 104: ......
Page 162: ......
Page 170: ...5 8 Compaq AlphaServer ES40 Service Guide Figure 5 4 FRU List Designator ...
Page 172: ...5 10 Compaq AlphaServer ES40 Service Guide Figure 5 5 Evidence Designator ...
Page 184: ...5 22 Compaq AlphaServer ES40 Service Guide Figure 5 7 Display Error Frames Screen ...
Page 193: ...Error Logs 5 31 Figure 5 14 Deleting an Old Error Frame ...
Page 194: ......
Page 280: ......
Page 310: ...8 30 Compaq AlphaServer ES40 Service Guide Figure 8 14 Aligning DIMM in MMB PK0953a ...
Page 332: ......
Page 336: ......
Page 358: ......
Page 444: ......