Brother P-touch PT-D600, Service Manual

Page: 168 / 171

APP 2 - 3
 Main PCB circuit diagram (3/5)
NAME
CODE
MAIN PCB CIR
PT-D600 (3/5)
AB[8]
AB[9]
AB[11]
AB[10]
AD[15]
AB[22]
AD[14]
AD[13]
AD[12]
AD[11]
AD[10]
AD[9]
AD[8]
AD[3]
AD[7]
AD[2]
AD[6]
AD[0]
AD[1]
AD[5]
AD[4]
AB[5]
AB[6]
AB[7]
AB[8]
AB[9]
AB[10]
AB[11]
AB[12]
AB[14]
AB[15]
AB[16]
AB[17]
AB[18]
AB[19]
AB[20]
AB[4]
AB[21]
AD[2]
AD[3]
AB[13]
AD[0]
AD[4]
AD[5]
AD[7]
AD[6]
AB[3]
AB[2]
AB[1]
AD[1]
AB[0]
AB[1]
AB[2]
AB[3] AB[4]
AB[6]
AB[5]
AB[7]
AB[12]
AB[14]
AB[16]
AB[17]
AB[15]
AB[13]
AB[24] 2F
AB[23] 2F
TP193
R93
10k
R102 33
GND
GND
R114
100
TP182
TP130
AB[23]
6B
TP192
TP161
2-2C FROM_AB[25]
AB[18]
2-7C/1F
GND
GND
3.3VCC
TP166
TP123
AB[24]
5C
TP195
3.3VCC
GND
R116
100
R95
10k
C121
C104
10VDC
3.3VCC
TP167
TP74
TP163
TP194
3.3VCC
FROM_CS2 1A
R117
100
3.3VCC
R112
10k
3.3VCC
TP124
TP178
GND
3.3VCC
C54
C103
25VDC
GND
R110
10k
C52
C103
25VDC
R94
10k
TP175
R107
10k
TP160
GND
GND
SRAM_CS
8C
AD[0-15]
2-5A/2-6A/2-7D/7E/4-1D
R57
10k
3.3VCC
TP174
R98
10k
TP162
3.3VCC
R90
10k
GND
AB[0-3]
2-8D/5D/4-1F/1F
3.3VCC
C51
C103
25VDC
R96
10k
TP176
C45
C104
10VDC
AB[1-22]
2-8D/5D/7E/2-7C/7C
3.3VCC
3.3VCC
AD[0-15]
2-5A/2-6A/2-7D/4F/4-1D
R118 10k
3.3VCC
TP191
R108
33
3.3VCC
GND
GND
RD
2-7C/1D/4-1F/4-1D
CS0_FROM
2-6B/5A/6B/6C
GND
3.3VCC
TP186
R111
10k
3.3VCC
C48
C103
25VDC
WR0
2-6D/1D/4-1F
CS0_FROM 2-6B/5A/5B/6B
2-2C FROM_AB[24]
R113
10k
TP184
GND
R109
100 C46
C103
25VDC
AB[0-17]
2-8D/7E/4-1F/1F/2-7C
CS0_FROM 2-6B/5A/5B/6C
RA22
33
2 7
1 8
3 6
4 5
GND
TP171
3.3VCC
R105
100
3.3VCC
RD
2-7C/6D/4-1F/4-1D
CS0_FROM
2-6B/5B/6B/6C
RA21
33
2 7
1 8
3 6
4
5
TP168
TP164
GND
GND
8B
FROM_CS2
WR0 2-6D/6D/4-1F
SRAM_CS 7D
RA18 33
2 7
1 8
3 6
4 5
TP170
TP188
R104 33
R91
10k
R89
10k
RESET
2-2C/4-4D
LCD_CS
4-1F
RA20
33
2 7
1 8
3 6
4 5
TP180
U13
CY62128EV30LL-45ZAXI
LW2606000
A11
25
A9
26
A8
27
A13
28
WE
29
CE2
30
A15
31
Vcc
32
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
OE
24
A10
23
CE1
22
I/O7
21
I/O6
20
I/O5
19
I/O4
18
I/O3
17
GND
16
I/O2
15
I/O1
14
I/O0
13
A0
12
A1
11
A2
10
A3
9
C53
C103
25VDC
R99
100
U14
74LVC1G19GW
A40476001
A
1
GND
2
E
3
Y0
6
Vcc
5
Y1
4
FROM_CS1 1D
8B
FROM_CS1
CS2_SRAM_LCD
2-5A
C47
C103
25VDC
RA19
33
2 7
1 8
3 6
4 5
R106
10k
3.3VCC
TP185
R92
10k
U15
74LVC1G19GW
A40476001
A
1
GND
2
E
3
Y0
6
Vcc
5
Y1
4
3.3VCC
RY/BY 2-6C
TP181
3.3VCC
R100 33
TP189
C50
C103
25VDC
TP165
GND
U12
74LVC2G08GT
A40473001
2
1B
7
1Y
8
VCC
3
2Y
4
GND
1
1A
6
2B
5
2A
U9
A63248001
S29GL256S90TFI020
CE
32
WE
13
OE
34
WP/ACC
16
BYTE
53
RESET
14
A0
31
A1
26
A2
25
A3
24
A4
23
A5
22
A6
21
A7
20
A8
10
A9
9
A10
8
A11
7
A12
6
A13
5
A14
4
A15
3
A16
54
A17
19
A18
18
A19
11
A20
12
A21
15
A22
2
A23
1
NC56
56
NC55
55
VCC
43
VIO
29
VSS_52
52
VSS_33
33
RY/BY
17
NC27
27
NC28
28
NC30
30
DQ0
35
DQ1
37
DQ2
39
DQ3
41
DQ4
44
DQ5
46
DQ6
48
DQ7
50
DQ8
36
DQ9
38
DQ10
40
DQ11
42
DQ12
45
DQ13
47
DQ14
49
DQ15/A-1
51
CS3_FROM 2-4A
TP173
C49
C103
25VDC
R103 33
TP190
TP187
TP177
TP179
U11
74LVC2G08GT
A40473001
2
1B
7
1Y
8
VCC
3
2Y
4
GND
1
1A
6
2B
5
2A
R97
100
2-6C FROM_AB[23]
TP159
U10
A63248001
S29GL256S90TFI020
CE
32
WE
13
OE
34
WP/ACC
16
BYTE
53
RESET
14
A0
31
A1
26
A2
25
A3
24
A4
23
A5
22
A6
21
A7
20
A8
10
A9
9
A10
8
A11
7
A12
6
A13
5
A14
4
A15
3
A16
54
A17
19
A18
18
A19
11
A20
12
A21
15
A22
2
A23
1
NC56
56
NC55
55
VCC
43
VIO
29
VSS_52
52
VSS_33
33
RY/BY
17
NC27
27
NC28
28
NC30
30
DQ0
35
DQ1
37
DQ2
39
DQ3
41
DQ4
44
DQ5
46
DQ6
48
DQ7
50
DQ8
36
DQ9
38
DQ10
40
DQ11
42
DQ12
45
DQ13
47
DQ14
49
DQ15/A-1
51
R101
33
TP169
GND
R115
100
TP183
TP128
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
256Mbit FROM
2Mbit: CY62138FV30LL-45ZAXI
1Mbit: CY62128EV30LL-45ZAXI
256Mbit FROM
Bank Switching Logic for FROM and Decoding logic SRAM
* In D600, either 1 FROM chip of 256MBit or both (256Mbit x 2) FROM chips will be
mounted based on the requirement.
FROM SECTION
SRAM 1Mbit / 2Mbit
1Mbit 32Pin STSOP