Register Map
AD1200 Reference
clock DMA requests and TTL i/o port pacer DMA requests
when the Extended Mode bits are set in the Timer Control
Register. When the Extended Mode bits are set the Pacer clock
is used to initiate the DMA cycle, the data is read from the TTL
input port or written to the TTL output port or the DAC0 or
DAC1 registers.
When
Set: DMA i/o is enabled and a DMA cycle with be
initiated due to A/D Done or Pacer Strobe depending
on the settings of the Mode Bit 1 and Mode bit 0
registers and the extended Mode bits of the Timer
Control register.
If Clear:
No DMA operations take place when this line is
clear, the DMA lines are tristated and the DMA
channel is free for use by other devices.
Set By:
This bit is set under program control.
Reset By: This is cleared under program control.
This bit is automatically cleared at power up.
Bit 2 Interrupt Enable, Read / Write.
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This bit is is used to enable interrupts, IRQs.
The whole range of AD1200 cards can generate A/D Done, and
A/D Error interrupts.
The top of range AD1200 card can also generate DAC0 and
DAC1 pacer clock interrupts and TTL i/o port pacer interrupts
when the Extended Mode bits are set.
When Set: Interrupts are generated when A/D Done bit or the
A/D Error bits is set.
AD1200 only: IRQ i/o due to A/D Done or Pacer
Strobes depending on combination of Mode Bits 0 &
1 and the Extended Mode bits in the Timer register.
If Clear:
No Interrupts are generated this bit is clear, the IRQ
lines are tristated and the IRQ channel is free for use
by other devices.
Set By:
This bit is set under program control.
Reset By: This is cleared under program control.
Chapter 3
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