Introduction
AD1200 Reference
will perform considerably worse than a 50MHz 486. The
efficiency of the code plays an important part in throughput
especially in the slower computers. In general it is almost
impossible to exceed 30,000 A/D conversion samples a second.
With the interrupt driven i/o, the time taken by the PC to
service the interrupt becomes the critical factor. Thus this part of
the software should merely increment a pointer to memory, read
the ADCLO and then ADCHI registers, then write the resulting
data word to the memory, select the next A/D channel and gain,
trigger the A/D converter to start the next conversion and finally
exit. The time taken for the PC to branch to this interrupt
service routine, perform it and return to its original task is,
again, a function of the PC’s clock speed and the size and
efficiency of the code written. The 2k FIFO on the AD1200
overcomes this difficulty and allows 100kHz sampling!
With DMA, the data from A/D converter is moved by the
DMA controller directly into the PC’s memory, and the PC’s
own processing power is unimportant, and the throughput of the
converter is at its maximum ie 30kHz for AD1221 and AD1211
or 100kHz for AD1220, AD1210 and AD1200.
For the higher A/D throughputs with interrupts or DMA
the pacer clock has to be used.
The pacer clock allows pipelining to be used. Pipelining is
when the NEXT conversion is taking place BEFORE the
previous one has been read. IE the next conversion is put into
the pipe before the previous one is taken out. This allows the
A/D converter to be constantly acquiring & converting inputs.
The data from the A/D converter can be read during the time
between successive conversions. It is necessary that an overrun
does not take place where the NEXT conversion is finished
BEFORE the previous conversion has been read. The circuitry in
the AD1200 series of cards is designed to make efficient use of
the Pipelining concept. Modes 1, 2 and 3 use the pacer clock to
pipeline the A/D conversions. The A/D Error bit will be set by
an A/D data overrun & the pacer clock will be stopped.
Chapter 1
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