Introduction
AD1200 Reference
IDC connector pin 49, starts the pacer clock running. The
first A/D strobe is generated one clock period later.
v)
When the A/D Done bit is set the ADCLO and ADCHI
data bytes may be read, either by programmed i/o, an
interrupt service routine or by the DMA controller.
vi)
A/D Strobes will be automatically generated by the pacer
clock at the chosen rate, based on the 600kHz oscillator,
until the clock is stopped by a write to the ADCSR or,
when using DMA, terminal count is reached.
Mode 3, Continuous Conversions, External Trigger & Clock.
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In Mode 3, the pacer clock generates each A/D strobe, the
clock is started, triggered, by a user supplied negative edge on
the external trigger input line. The fundamental frequency of the
the pacer clock is derived from a user supplied external clock,
on IDC Connector pin 50. The following method should be used.
Mode 3 allows the a series of conversions to be synchronised
with external events or to an external device.
i)
The mode bits in the ADCSR, A/D Control Status
Register, register 0, should be set to 03, ie Mode 3.
This stops the pacer clock if it is running.
ii)
The pacer clock divisor, determining the frequency of the
pacer clock strobes, is written to the TIMER register. Bits
6 & 7 must be zero in the AD1200 card.
iii)
The channel and gain required is written into the ADGCR,
A/D Gain Channel register, register 1.
iv)
A negative edge on the user supplied external trigger input,
IDC connector pin 49, starts the pacer clock running. The
first A/D strobe is generated one clock period later.
v)
When the A/D Done bit is set the ADCLO and then the
ADCHI data bytes may be read, either by programmed i/o,
an interrupt service routine or by the DMA controller.
vi)
A/D Strobes will be automatically generated by the pacer
clock at the chosen rate, based on the user supplied
external clock input, until the clock is stopped by a write
to the ADCSR or, when using DMA, terminal count is
reached.
Chapter 1
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