AD1200 Reference
Introduction
Mode 1, Continuous Conversions, Internal Trigger & Clock.
____________________________________________________
In Mode 1, the pacer clock generates each A/D strobe, the
clock is started, triggered, by a write to the ADGCR, the A/D
Gain Channel Register, register 1. The following method should
be used.
i)
The mode bits in the ADCSR, A/D Control Status
Register, register 0, should be set to 01, ie Mode 1.
This stops the pacer clock if it is running.
ii)
The pacer clock divisor, determining the frequency of the
pacer clock strobes, is written to the TIMER register. Bits
6 & 7 must be zero in the AD1200 card.
iii)
The channel and gain required is written into the ADGCR,
A/D Gain Channel register, register 1. This starts the pacer
clock running. The first A/D strobe is generated one clock
period later.
iv)
When the A/D Done bit is set the ADCLO and then the
ADCHI data bytes may be read, either by programmed i/o,
an interrupt service routine or by the DMA controller.
v)
A/D Strobes will be automatically generated by the pacer
clock at the chosen rate, based on the 600kHz oscillator,
until the clock is stopped by a write to the ADCSR or,
when using DMA, terminal count is reached.
Mode 2, Continuous Conversions, Ext Trig, Internal Clock.
___________________________________________________
In Mode 2, the pacer clock generates each A/D strobe, the
clock is started, triggered, by a user supplied negative edge on
the external trigger input line. The following method should be
used. Mode 2 allows external devices to initiate a series of
conversions.
i)
The mode bits in the ADCSR, A/D Control Status
Register, register 0, should be set to 02, ie Mode 2.
This stops the pacer clock if it is running.
ii)
The pacer clock divisor, determining the frequency of the
pacer clock strobes, is written to the TIMER register. Bits
6 & 7 must be zero in the AD1200 card.
iii)
The channel and gain required is written into the ADGCR,
A/D Gain Channel register, register 1.
iv)
A negative edge on the user supplied external trigger input,
Page 18
Chapter 1
