AD1200 Reference
Register Map
Reset By: Reading the ADC data high byte at Register 3.
This bit is automatically cleared at power up.
Bit 6 A/D Error, Read Only.
_________________________
This bit is indicates that an error has occurred during the
A/D conversion.
Set By:
Overrun error. A new conversion has been completed
whilst the previous has not been read, ie ADCHI,
Register 3 has not been read.
Trigger error. A new conversion has been requested
while the current conversion is in progress.
If Bit 2, Interrupt Enable, of the ADCSR is also set,
then an interrupt will be generated when this bit is
set by the ADC.
Reset By: Writing a 1 to bit 4 of the ADCSR.
This bit is automatically cleared at power up.
Bit 5 A/D Busy, Read Only.
________________________
This bit is indicates that an A/D conversion is in progress.
Set By:
An A/D strobe. Any further A/D strobes while this
bit is set will cause an A/D error due to overrun.
Reset
By: This bit is automatically cleared when the A/D
conversion is finished and the data is ready to be
read from the ADCLO and ADCHI registers.
Bit 4 Clear A/D Error, Write Only.
______________________________
_
Writing a 1 to this bit clears the A/D Error bit, bit 6 of the
ADCSR.
Note: This bit ALWAYS reads back as 0.
Bit 3 DMA Enable, Read / Write.
AD1200 Only
_____________________________
____________
This bit is used to enable DMA on the AD1200 card only.
This bit is always reads as 0 on the AD1210, AD1211, AD1220
and AD1221 cards since these do not have DMA capability.
The top of range AD1200 card can card perform DMA on
A/D Conversion Done and also generate DAC0 and DAC1 pacer
Page 54
Chapter 3
