Avaya 1000 Series, Reference

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Digital phase lock loops
The main digital PLL enables the clock controller to provide a system clock to the CPU. This
clock is both phase and frequency locked to a known incoming reference.
The hardware has a locking range of + 4.6 ppm for Stratum 3 and + 50 ppm for Stratum 4
(CCITT).
A second PLL on the clock controller provides the means for monitoring another reference.
Note that the error signal of this PLL is routed to the phase difference detector circuit so the
microprocessor can process it.
System clock specification and characteristics
As the accuracy requirements for CCITT and EIA Stratum 3 are different, it is necessary to
have two TCVCXOs which feature different values of frequency tuning sensitivity. See
Table
225: System clock specification and characteristics on page 517.
Table 225: System clock specification and characteristics
Specifications CCITT EIA
Base Frequency 20.48 MHz 20.48 MHz
Accuracy ±3 ppm ±1 ppm
Operating Temperature 0 to 70 C ±1 ppm 0 to 70 C ±1 ppm
Drift Rate (Aging) ±1 ppm per year ±4 ppm in 20 years
Tuning Range (minimum) ±60 ppm min. ±10 ppm min.
±90 ppm max. ±15 ppm max.
Input Voltage Range 0 to 10 volts, 5 V center 0 to 10 volts, 5 V center
EIA/CCITT compliance
The clock controller complies with 1.5 Mb EIA Stratum 3ND, 2.0 Mb CCITT or 2.56 Mb basic
rate. The differences between these requirements mainly affect PLL pull in range. Stratum 4
conforms to international markets (2.0 Mb) while Stratum 3 conforms to North American
markets (1.5 Mb).
Functional description
Circuit Card Reference July 2011 517