Avaya 1000 Series, Reference

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The digital pad provides gain or attenuation values to condition the level of the digitized
transmission signal according to the network loss plan. This sets transmission levels for the
B-channel circuit-switched voice calls.
The clock recovery circuit recovers the clock from the local exchange.
The clock converter converts the 5.12 MHz clock from the IPE backplane into a 2.56 MHz clock
to time the IPE bus channels and an 8 kHz clock to provide PCM framing bits.
The PE interface logic consists of a Card-LAN interface, a PE bus interface, a maintenance
signaling channel interface, a digital pad, and a clock controller and converter.
The Card-LAN interface is used for routine card maintenance, which includes polling the line
cards to find the card slot where the SILC is installed. It also queries the status and identification
of the card and reports the configuration data and firmware version of the card.
The PE bus interface connects one PE bus loop that has 32 channels operating at 64 kbps
and one additional validation and signaling bit.
The Maintenance Signaling Channel (MSC) interface communicates signaling and card
identification information from the CS 1000CPU to the SILC MCU. The signaling information
also contains maintenance instructions.
The digital pad provides gain or attenuation values to condition the level of the digitized
transmission signal according to the network loss plan. This sets transmission levels for the
B-channel voice calls.
The clock recovery circuit recovers the clock from the local exchange.
The clock converter converts the 5.12-MHz clock from the PE backplane into a 2.56-MHz clock
to time the PE bus channels and an 8-kHz clock to provide PCM framing bits.
S/T interface logic
The S/T interface logic consists of a transceiver circuit and the DSL power source. This
interface supports DSLs of different distances and different numbers and types of terminal.
The transceiver circuits provide four-wire full-duplex S/T bus interface. This bus supports
multiple physical terminations on one DSL where each physical termination supports multiple
logical B-channel and D-channel ISDN BRI terminals. Idle circuit-switched B-channels can be
allocated for voice or data transmission to terminals making calls on a DSL. When those
terminals become idle, the channels are automatically made available to other terminals
making calls on the same DSL.
The power on the DSL comes from the SILC, which accepts –48 V from the IPE backplane
and provides two watts of power to physical terminations on each DSL. It provides -48 V for
ANSI-compliant ISDN BRI terminals and –40 V for CCITT (such as ETSI NET-3, INS NET-64)
compliant terminals. The total power used by the terminals on each DSL must not exceed two
watts.The S/T interface logic consists of a transceiver circuit and the DSL power source. This
interface supports DSLs of different distances and different number and types of terminals.
Functional description
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