Avaya 1000 Series, Reference

Page: 516 / 700

Table 224: Faceplate LEDs
State Definition
On (Red) NTAK20 is equipped and disabled.
On (Green) NTAK20 is equipped, enabled, and is either locked to a reference or is in
free run mode.
Flashing
(Green) NTAK20 is equipped and is attempting to lock (tracking mode) to a
reference. If the LED flashes continuously over an extended period of
time, check the CC STAT in LD 60. If the CC is tracking this may be an
acceptable state. Check for slips and related clock controller error
conditions. If none exist, then this state is acceptable, and the flashing is
identifying jitter on the reference.
Off NTAK20 is not equipped.
Functional description
The main functional blocks of the NTAK20 architecture include:
• phase difference detector circuit
• digital Phase Locked Loop (PLL)
• clock detection circuit
• digital-to-analog converter
• CPU MUX bus interface
• signal conditioning drivers and buffers
• sanity timer
• microprocessor
• CPU interface
• external timing interface
Phase difference detector circuit
This circuit, under firmware control, enables a phase difference measurement to be taken
between the reference entering the PLL and the system clock.
The phase difference is used for making frequency measurements and evaluating input jitter
and PLL performance.
NTAK20 Clock Controller daughterboard
516 Circuit Card Reference July 2011
Comments? infodev@avaya.com