AutomationDirect DL105, User Manual

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High
-S
peed
Input
and
Pulse
O
utput
Features
3--6
High-speed Input and Pulse Output Features
DL105 PLC User Manual, 3rd Edition
Mode 10: High-Speed Counter
The HSIO circuit contains one high-speed counter. A single pulse train from an
external source (X0) clocks the counter on each signal leading edge. The counter
counts only upwards, from 0 to 99999999. The counter compares the current count
with up to 24 preset values, which you define. The purpose of the presets is to quickly
cause an action upon arrival at specific counts, making it ideal for such applications
as cut-to-length. It uses counter registers CT76 and CT77 in the CPU.
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “10”, the high-speed up counter in the HSIO circuit is enabled. X0
automatically becomes the “clock” input for the high-speed counter, incrementing it
upon each off-to-on transition. The external reset input on X2 is the default
configuration for Mode 10. Inputs X1 and X3 are filtered inputs, available to the
ladder program.
Output Circuit
Input Circuit
CPU
PLC
DL105
X0
Y0, Y1
X4-- X11
Y2 -- Y7
V-memory
V7633 xx10
Mode Select
I/O data
HSIO
COUNTER
CLK Reset
X2 X1, X3
FILTER
Instead of using X2 as a dedicated reset input, you can configure X2 as a normal
filtered input. In this way, the counter reset must be generated in ladder logic.
Output Circuit
Input Circuit
CPU
PLC
DL105
X0
Y0, Y1
X4-- X11
Y2 -- Y7
V-memory
V7633 xx10
Mode Select
I/O data
HSIO
COUNTER
CLK
Reset
X1, X2, X3
FILTER
Next, we will discuss how to program the high-speed counter and its presets.
Purpose
Functional Block
Diagram