253
8210C–AVR–09/11
Atmel AVR XMEGA D
21.9.1
Single Conversion without Gain
shows the ADC timing for a single conversion without gain. The writ-
ing of the start conversion bit, or the event triggering the conversion (START), must occur at
least one peripheral clock cycle before the ADC clock cycle on which the conversion starts (indi-
cated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 21-13.
ADC timing for one single conversion without gain.
Figure 21-14.
ADC timing for one single conversion with increased sampling time (SAMPVAL = 6).
21.9.2
Single Conversion with Gain
show the ADC timing for one single con-
version with various gain settings. As seen in the
, the gain stage is built
into the ADC. Gain is achieved by running the signal through a pipeline stage without converting.
Compared to a conversion without gain, each gain multiplication of 2 adds one half ADC clock
cycle to.
clk
ADC
START
ADC SAMPLE
IF
CONVERTING BIT
10
9
8
7
6
5
4
3
2
1
lsb
1
2
3
4
5
6
7
8
msb
9
IF
CONVERTING BIT
10
9
8
7
6
5
4
3
2
1
lsb
msb
CONVERTING BIT
START
IF
ADC SAMPLE
msb
10
9
8
7
6
5
4
3
2
1
lsb
clk
ADC
1
2
3
4
5
6
7
8
9
10