manualshive.com logo in svg

Atmel AVR XMEGA D Series, Manual, Page: 225 / 331

Share
Download
Atmel AVR XMEGA D Series Manual Download Page 225

225

8210C–AVR–09/11

Atmel AVR XMEGA D

• Interrupt timing is not compatible

• Pin control differs due to the master-only operation of the USART in SPI master mode

A comparison of the USART in master SPI mode and the SPI pins is shown 

Table 18-5

.

18.12 Multiprocessor Communication Mode

The multiprocessor communication mode effectively reduces the number of incoming frames
that have to be handled by the receiver in a system with multiple microcontrollers communicat-
ing via the same serial bus. In this mode, a dedicated bit in the frames is used to indicate
whether the frame is an address or data frame type.

If the receiver is set up to receive frames that contain five to eight data bits, the first stop bit is
used to indicate the frame type. If the receiver is set up for frames with nine data bits, the ninth
bit is used. When the frame type bit is one, the frame contains an address. When the frame type
bit is zero, the frame is a data frame. If 5-bit to 8-bit character frames are used, the transmitter
must be set to use two stop bits, since the first stop bit is used for indicating the frame type.

If a particular slave MCU has been addressed, it will receive the following data frames as usual,
while the other slave MCUs will ignore the frames until another address frame is received.

18.12.1

Using Multiprocessor Communication Mode

The following procedure should be used to exchange data in multiprocessor communication
mode (MPCM):

1.

All slave MCUs are in multiprocessor communication mode.

2.

The master MCU sends an address frame, and all slaves receive and read this frame.

3.

Each slave MCU determines if it has been selected.

4.

The addressed MCU will disable MPCM and receive all data frames. The other slave 
MCUs will ignore the data frames.

5.

When the addressed MCU has received the last data frame, it must enable MPCM 
again and wait for a new address frame from the master.

The process then repeats from step 2.

Using any of the 5-bit to 8-bit character frame formats is impractical, as the receiver must
change between using n and n+1 character frame formats. This makes full-duplex operation dif-
ficult, since the transmitter and receiver must use the same character size setting.

18.13 IRCOM Mode of Operation

IRCOM mode can be enabled to use the IRCOM module with the USART. This enables IrDA 1.4
compliant modulation and demodulation for baud rates up to 115.2kbps. When IRCOM mode is
enabled, double speed mode cannot be used for the USART.

Table 18-5.

Comparison of USART in master SPI mode and SPI pins.

USART

SPI

Comment

TxD

MOSI

Master out only

RxD

MISO

Master in only

XCK

SCK

Functionally identical

N/A

SS

Not supported by USART in master SPI mode

Summary of Contents for AVR XMEGA D Series

Page 1: ...reset WDT Watchdog timer Interrupts and programmable multilevel interrupt controller PORT I O ports TC 16 bit timer counter AWeX Advanced waveform extension Hi Res High resolution extension RTC Real...

Page 2: ...on sections list all registers and describe each register bit and flag with their function This includes details on how to set up and enable various features in the module When multiple bits are neede...

Page 3: ...fast two pin interface for programming and debug ging is available The Atmel AVR XMEGA D devices have five software selectable power saving modes The idle mode stops the CPU while allowing the event...

Page 4: ...Prog Debug Controller VCC GND PORT R 2 XTAL1 XTAL2 PR 0 1 TOSC1 TOSC2 PQ 0 7 Oscillator Circuits Clock Generation Oscillator Control Real Time Counter Event System Controller PDI_DATA RESET PDI_CLK S...

Page 5: ...o access memories perform calculations control peripherals and execute the program in the flash memory Interrupt han dling is described in a separate section Interrupts and Programmable Multilevel Int...

Page 6: ...from SRAM is not supported It can easily be accessed through the five different addressing modes supported in the AVR architecture The first SRAM address is 0x2000 Data addresses 0x1000 to 0x1FFF are...

Page 7: ...bit format During interrupts and subroutine calls the return address PC is stored on the stack The stack is allocated in the general data SRAM and consequently the stack size is only limited by the t...

Page 8: ...always points to the top of the stack It is implemented as two 8 bit registers that are accessible in the I O memory space Data are pushed and popped from the stack using the PUSH and POP instructions...

Page 9: ...register pointers for data space addressing enabling efficient address calculations One of these address pointers can also be used as an address pointer for lookup tables in flash program memory Figu...

Page 10: ...ata memory space in the device is implemented in the registers 3 10 1 RAMPZ Registers The RAMPZ registers are concatenated with the X Y and Z registers respectively to enable indirect addressing of th...

Page 11: ...11 1 Accessing 24 and 32 bit Registers For 24 and 32 bit registers the read and write access is done in the same way as described for 16 bit registers except there are two temporary registers for 24 b...

Page 12: ...he duration of the configuration change enable period Any interrupt request including non maskable interrupts during the CCP period will set the corresponding interrupt flag as normal and the request...

Page 13: ...loca tions above the first 64KB and writing SPM program memory locations above the first 128KB of the program memory This register is not available if the program memory in the device is less than 64...

Page 14: ...disable interrupts for the next four instructions or until the next I O mem ory write Only the number of bits required to address the available data memory including external mem ory up to 64KB is imp...

Page 15: ...bit in a register in the register file by the BLD instruction Bit 5 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations Half carry Is useful in BCD arithmetic...

Page 16: ...3 Bit 2 Bit 1 Bit 0 Page 0x00 Reserved 0x01 Reserved 0x02 Reserved 0x03 Reserved 0x04 CCP CCP 7 0 13 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 Reserved 0x09 Reserved 0x0A Reserved 0x0B RAMPZ RAMP...

Page 17: ...ipherals User signature row One flash page in size Can be read and written from software Content is kept after chip erase 4 2 Overview This section describes the different memories in XMEGA AU devices...

Page 18: ...level for the application section can be selected by the boot lock bits for this section The application section can not store any boot loader code since the SPM instruction cannot be executed from th...

Page 19: ...ible read and write from application software and external programmers It is one flash page in size and is meant for static user parameter storage such as calibration data custom serial number identif...

Page 20: ...fer loading When doing this EEPROM is accessible using load and store instructions Memory mapped EEPROM will always start at hexadecimal address 0x1000 4 8 I O Memory The status and configuration regi...

Page 21: ...d the device type A separate register contains the revision number of the device 4 11 I O Memory Protection Some features in the device are regarded as critical for safety in some applications Due to...

Page 22: ...This register gives the address extended byte when accessing NVM locations 4 12 4 DATA0 Data register 0 The DATA0 DATA1 and DATA registers represent the 24 bit value DATA This holds data dur ing NVM r...

Page 23: ...ands for the flash Bit 6 is only set for external pro gramming commands See Memory Programming on page 294 for programming commands 4 12 8 CTRLA Control register A Bit 7 1 Reserved These bits are unus...

Page 24: ...the CPU will be halted for a time equal to the start up time from the idle sleep mode Bit 1 EPRM EEPROM Power Reduction Mode Setting this bit enables power saving for the EEPROM The EEPROM will then...

Page 25: ...ed Once an operation is started this flag is set and remains set until the operation is completed The NVMBUSY flag is automati cally cleared when the operation is finished Bit 6 FBUSY Flash Busy The F...

Page 26: ...ing of the NVM lockbits into the I O memory space enable direct read access from the application software Refer to LOCKBITS Lock Bit register on page 30 for description Bit 7 6 5 4 3 2 1 0 0x07 BLBB 1...

Page 27: ...used and reserved for future use For compatibility with future devices always write this bit to one when this register is written Bit 6 BOOTRST Boot Loader Section Reset Vector This fuse can be progra...

Page 28: ...ality When this is done pulling th pin low will not cause an external reset A reset is required before this bit will be read correctly after it is changed Bit 3 2 STARTUPTIME 1 0 Start up time These f...

Page 29: ...SEBYTE5 Fuse Byte 5 Bit 7 6 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to one when this register is written Bit 5 4 BODACT...

Page 30: ...2 0 BODLEVEL 2 0 Brownout Detection Voltage Level These fuse bits sets the BOD voltage level Refer to Reset System on page 87 for details For BOD level nominal values see Table 8 2 on page 90 4 13 5 L...

Page 31: ...er section and E LPM executing from the application section is not allowed to read from the boot loader section If the interrupt vectors are placed in the application section interrupts are disabled w...

Page 32: ...ecuting from the boot loader section is not allowed to read from the application table section If the interrupt vectors are placed in the boot loader section interrupts are disabled while executing fr...

Page 33: ...production test of the device During reset this value is auto matically loaded into calibration register A for the 2MHz DFLL Refer to CALB DFLL Calibration register B on page 76 for more details 4 14...

Page 34: ...roduction test of the device During reset this value is auto matically loaded into calibration register A for the 32MHz DFLL Refer to CALA DFLL Calibration Register A on page 75 for more details 4 14...

Page 35: ...Bit 7 0 LOTNUM4 7 0 Lot Number Byte 4 This byte contains byte 4 of the lot number for the device 4 14 11 LOTNUM5 Lot Number register 5 Bit 7 0 LOTNUM5 7 0 Lot Number Byte 5 This byte contains byte 5 o...

Page 36: ...wafer coordinate X for the device 4 14 14 COORDX1 Wafer Coordinate X register 1 Bit 7 0 COORDX0 7 0 Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device 4 14 15 CO...

Page 37: ...s byte 1 of the ADCA calibration data and must be loaded into the ADCA CALH register 4 14 19 ADCBCAL0 ADCB Calibration register 0 ADCBCAL0 and ADCBCAL1 contains the calibration value for the analog to...

Page 38: ...used for single or multi point temperature sensor calibration Bit 7 0 TEMPSENSE0 7 0 Temperature Sensor Calibration Byte 0 This byte contains the byte 0 of the temperature measurement 4 14 22 TEMPSENS...

Page 39: ...will always be read as 0x1E This indicates that the device is manufactured by Atmel 4 16 2 DEVID1 Device ID register 1 Bit 7 0 DEVID 7 0 Device ID Byte 1 Byte 1 of the device ID indicates the flash si...

Page 40: ...this is done the internal compo nents such as voltage reference and bias currents are started sequentially when the module is enabled This reduces the peak current consumption during startup of the mo...

Page 41: ...ction mechanism For details refer to Configuration Change Protec tion on page 11 4 16 7 AWEXLOCK Advanced Waveform Extension Lock register Bit 7 1 Reserved These bits are unused and reserved for futur...

Page 42: ...ved 0x09 Reserved 0x0A CMD CMD 6 0 26 0x0B CTRLA CMDEX 27 0x0C CTRLB EEMAPEN FPRM EPRM SPMLOCK 27 0x0D INTCTRL SPMLVL 1 0 EELVL 1 0 28 0x0E Reserved 0x0F STATUS NVMBUSY FBUSY EELOAD FLOAD 28 0x10 LOCK...

Page 43: ...M 7 0 38 0x11 Reserved 0x12 NO COORDX0 COORDX0 7 0 36 0x13 NO COORDX1 COORDX1 7 0 36 0x14 NO COORDY0 COORDY0 7 0 36 0x15 NO COORDY1 COORDY1 7 0 37 0x16 Reserved 0x17 Reserved 0x18 Reserved 0x19 Reserv...

Page 44: ...it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 DEVID0 DEVID0 7 0 39 0x01 DEVID1 DEVID1 7 0 39 0x02 DEVID2 DEVID2 7 0 39 0x03 REVID REVID 3 0 40 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 ANAIN...

Page 45: ...provide a predictable system for short and predictable response times between peripherals It allows for autonomous peripheral control and interaction without the use of inter rupt or CPU resources and...

Page 46: ...hange of state within a peripheral has occurred is called an event There are two main types of events signaling events and data events Signaling events only indicate a change of state while data event...

Page 47: ...an also use signaling events This is configurable and is described in the datasheet module for each peripheral 5 3 3 Peripheral Clock Events Each event channel includes a peripheral clock prescaler wi...

Page 48: ...tiplex ers CHnMUX which can each be configured to route any event source to any event users The output from a multiplexer is referred to as an event channel For each peripheral it is selectable if and...

Page 49: ...in all peripherals This only means that a peripheral is not available for generating or using events The network configuration itself is compatible between all devices 48 PORTA PORTB PORTC PORTD PORTE...

Page 50: ...ded for pin change events 5 7 Quadrature Decoder The event system includes one quadrature decoder QDEC which enable the device to decode quadrature input on I O pins and send data events that a timer...

Page 51: ...l index count The following procedure should be used for QDEC setup 1 Choose two successive pins on a port as QDEC phase inputs 2 Set the pin direction for QDPH0 and QDPH90 as input 3 Set the pin conf...

Page 52: ...ut clock prescaling The angle of a quadrature encoder attached to QDPH0 QDPH90 and QINDX can now be read directly from the timer counter count register If the count register is different from BOTTOM w...

Page 53: ...ister is zero Bit 7 6 5 4 3 2 1 0 CHnMUX 7 0 CHnMUX Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table 5 3 CHnMUX 7 0 bit settings CHnMUX 7 4 CHnMUX 3 0 Group Configuration...

Page 54: ...X X X Reserved 0101 0 n PORTA_PINn 1 PORTA pin n n 0 1 2 or 7 0101 1 n PORTB_PINn 1 PORTB pin n n 0 1 2 or 7 0110 0 n PORTC_PINn 1 PORTC pin n n 0 1 2 or 7 0110 1 n PORTD_PINn 1 PORTD pin n n 0 1 2 or...

Page 55: ...cycles defined by DIGFILT 5 8 3 STROBE Strobe register If the STROBE register location is written each event channel will be set according to the STROBE n and corresponding DATA n bit settings if any...

Page 56: ...ntains the data value when manually generating a data event This register must be written before the STROBE register For details See STROBE Strobe register on page 55 Bit 7 6 5 4 3 2 1 0 0x11 DATA 7 0...

Page 57: ...X CH1MUX 7 0 53 0x02 CH2MUX CH2MUX 7 0 53 0x03 CH3MUX CH3MUX 7 0 53 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 CH0CTRL QDIRM 1 0 QDIEN QDEN DIGFILT 2 0 54 0x09 CH1CTRL DIGFILT 2 0 54...

Page 58: ...al oscillators and external crystal oscillator and resonator sup port A high frequency phase locked loop PLL and clock prescalers can be used to generate a wide range of clock frequencies A calibratio...

Page 59: ...AM AVR CPU Non Volatile Memory Watchdog Timer Brown out Detector System Clock Prescalers System Clock Multiplexer SCLKSEL PLLSRC RTCSRC DIV32 32 kHz Int ULP 32 768 kHz Int OSC 32 768 kHz TOSC 2 MHz In...

Page 60: ...rest of the clocks are stopped 6 4 Clock Sources The clock sources are divided in two main groups internal oscillators and external clock sources Most of the clock sources can be directly enabled and...

Page 61: ...or automatic run time calibration of the oscillator to compensate for tem perature and voltage drift and optimize the oscillator accuracy 6 4 2 External Clock Sources The XTAL1 and XTAL2 pins can be u...

Page 62: ...table from software and can be changed during normal operation Built in hardware protection prevents unsafe clock switching It is not possible to select a non stable or disabled oscillator as the cloc...

Page 63: ...1 to 31 The output frequency fOUT is given by the input frequency fIN multiplied by the multiplication factor PLL_FAC Four different clock sources can be chosen as input to the PLL 2MHz internal osci...

Page 64: ...e a 1 024kHz reference The refer ence clock is individually selected for each DFLL as shown on Figure 6 6 on page 64 Figure 6 6 DFLL reference clock selection The ideal counter value representing the...

Page 65: ...software for man ual run time calibration of the oscillator 6 8 PLL and External Clock Source Failure Monitor A built in failure monitor is available for the PLL and external clock source If the failu...

Page 66: ...next reset The failure monitor is stopped in all sleep modes where the PLL or external clock source are stopped During wake up from sleep it is automatically restarted The PLL and external clock sour...

Page 67: ...changed if the new clock source is not stable 6 9 2 PSCTRL Prescaler register This register is protected by the configuration change protection mechanism For details refer to Configuration Change Pro...

Page 68: ...frequency for the ClkPER and ClkCPU clocks relative to the ClkPER2 clock Refer to Figure 6 5 on page 63 fore more details Table 6 2 Prescaler A division factor PSADIV 4 0 Group Configuration Descript...

Page 69: ...bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bit 3 1 RTCSRC 2 0 RTC Clock Source These bits select th...

Page 70: ...lowed time to stabilize before it is selected as the source for the system clock See STATUS Oscillator Status register on page 71 Bit 2 RC32KEN 32 768kHz Internal Oscillator Enable Setting this bit en...

Page 71: ...ready to be used as the system clock source Bit 1 RC32MRDY 32MHz Internal Oscillator Ready This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the sys tem clock s...

Page 72: ...guration cannot be changed Notes 1 This option should be used only when frequency stability at startup is not important for the application The option is not suitable for crystals 2 This option is int...

Page 73: ...ll clear XOSCFDIF Bit 0 XOSCFDEN Failure Detection Enable Setting this bit will enable the failure detection monitor and a non maskable interrupt will be issued when XOSCFDIF is set This bit is protec...

Page 74: ...For compatibility with future devices always write these bits to zero when this register is written Bit 2 1 RC32MCREF 1 0 32MHz Oscillator Calibration Reference These bits are used to select the calib...

Page 75: ...itten Bit 0 ENABLE DFLL Enable Setting this bit enables the DFLL and auto calibration of the internal oscillator 6 11 2 CALA DFLL Calibration Register A The CALA and CALB registers hold the 13 bit DFL...

Page 76: ...t is used to select the oscillator fre quency A factory calibrated value is loaded from the signature row of the device and written to this register during reset giving an oscillator frequency approxi...

Page 77: ...2 1 0 0x06 COMP 15 8 COMP2 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table 6 9 Nominal DFLL32M COMP values for different output frequencies Oscillator Frequency MHz COM...

Page 78: ...01 STATUS PLLRDY XOSCRDY RC32KRDY R32MRDY RC2MRDY 70 0x02 XOSCCTRL FRQRANGE 1 0 X32KLPM XOSCPWR XOSCSEL 3 0 71 0x03 XOSCFAIL PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN 73 0x04 RC32KCAL RC32KCAL 7 0 73 0x05 PLL...

Page 79: ...ipherals from software When this is done the current state of the peripheral is frozen and there is no power consumption from that peripheral This reduces the power consumption in active mode and idle...

Page 80: ...roller and event system are kept running Any enabled interrupt will wake the device 7 3 2 Power down Mode In power down mode all clocks including the real time counter clock source are stopped This al...

Page 81: ...tion in an AVR MCU controlled system In general correct sleep modes should be selected and used to ensure that only the modules required for the application are operating All unneeded functions should...

Page 82: ...power Refer to WDT Watchdog Timer on page 95 for details on how to configure the watch dog timer 7 5 5 Port Pins When entering a sleep mode all port pins should be configured to use minimum power Most...

Page 83: ...ted To avoid unintentional entering of sleep modes it is recommended to write SEN just before executing the SLEEP instruction and clear it immediately after waking up 7 7 Register Description Power Re...

Page 84: ...e use For compatibility with future devices always write this bit to zero when this register is written 7 7 2 PRPA Power Reduction Port A register Note Disabling of analog modules stops the clock to t...

Page 85: ...d to ensure proper operation Bit 3 SPI Serial Peripheral Interface Setting this bit stops the clock to the SPI When this bit is cleared the peripheral should be rein itialized to ensure proper operati...

Page 86: ...Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 CTRL SMODE 2 0 SEN 83 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 PRGEN RTC EVSYS 83 0x01 PRPA ADC AC 84 0x02 Reserved 0x...

Page 87: ...e immediately tri stated The program counter is set to the reset vector location and all I O registers are set to their initial values The SRAM content is kept However if the device accesses the SRAM...

Page 88: ...when all reset requests are released The reset delay is timed from the 1kHz output of the ultra low power ULP internal oscillator and in addition 24 System clock clkSYS cycles are counted before reset...

Page 89: ...VPOT and this will start the reset sequence The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level The VPOT level is higher for falling VCCthan f...

Page 90: ...ll detect a drop in VCC only if the voltage stays below the trigger level for lon ger than tBOD Figure 8 4 Brownout detection reset For BOD characterization data consult the device datasheet The progr...

Page 91: ...mode while the BODPD fuse determines the brownout detection setting for all sleep modes except idle mode 8 4 3 External Reset The external reset circuit is connected to the external RESET pin The ext...

Page 92: ...er The reset will be issued within two CPU clock cycles after writing the bit It is not possible to execute any instruction from when a software reset is requested until it is issued Figure 8 7 Softwa...

Page 93: ...curs The flag will be cleared by a power on reset or by writ ing a one to the bit location Bit 1 EXTRF External Reset Flag This flag is set if an external reset occurs The flag will be cleared by a po...

Page 94: ...94 8210C AVR 09 11 Atmel AVR XMEGA D 8 6 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 STATUS SRF PDIRF WDRF BORF EXTRF PORF 93 0x01 CTRL SWRST 93...

Page 95: ...h WDT must be reset If the WDT is reset outside this window either too early or too late a system reset will be issued Compared to the normal mode this can also catch sit uations where a code error ca...

Page 96: ...the total duration of the time out period is the sum of the closed window and the open window timeout periods The default closed window timeout period is controlled by fuses both open and closed peri...

Page 97: ...er Bits 7 6 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bits 5 2 PER 3 0 Timeout Peri...

Page 98: ...Window Mode Control register Bit 7 6 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bit...

Page 99: ...TRL Window Mode Control register on page 98 When writing a new value to this register this bit must be written to one at the same time for the changes to take effect This bit is protected by the confi...

Page 100: ...rom the system clock to the WDT clock domain This bit is automatically cleared after the synchronization is finished Synchronization will take place only when the ENABLE bit for the Watchdog Timer is...

Page 101: ...ritizing of interrupt requests When an interrupt request is acknowl edged by the PMIC the program counter is set to point to the interrupt vector and the interrupt handler can be executed All peripher...

Page 102: ...mory space is the reset vector All inter rupts are assigned individual control bits for enabling and setting the interrupt level and this is set in the control registers for each peripheral that can g...

Page 103: ...same time priority is static according to the interrupt vector address where the lowest address has highest priority 10 4 2 Interrupt Response Time The interrupt response time for all the enabled int...

Page 104: ...ion response time is increased by five clock cycles In addition the response time is increased by the start up time from the selected sleep mode A return from an interrupt handling routine takes four...

Page 105: ...is decided both by the level and the pri ority of the interrupt request Interrupts can be organized in a static or dynamic round robin priority scheme High and medium level interrupts and the NMI wil...

Page 106: ...enabled the interrupt vector address for the last acknowledged low level interrupt will have the lowest priority the next time one or more interrupts from the low level is requested Figure 10 4 Round...

Page 107: ...t Executing This flag is set when a high level interrupt is executing or when the interrupt handler has been interrupted by an NMI The flag will be cleared when returning RETI from the interrupt handl...

Page 108: ...cleared zero the interrupt vectors are placed at the start of the applica tion section in flash When this bit is set one the interrupt vectors are placed in the beginning of the boot section of the f...

Page 109: ...t is cleared low level interrupt requests will be ignored Note 1 Ignoring interrupts will be effective one cycle after the bit is cleared 10 9 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 110: ...ontrollers have flexible general purpose I O ports One port consists of up to eight port pins pin 0 to 7 Each port pin can be configured as input or output with configurable driver and pull settings T...

Page 111: ...ritten to one pin n is configured as an output pin If DIRn is written to zero pin n is configured as an input pin When direction is set as output the OUTn bit in OUT is used to set the value of the pi...

Page 112: ...onfiguration is configured through the pin configuration register all intermediate port states during switching of the pin direction and pin values are avoided The I O pin configurations are summarize...

Page 113: ...1 the bus keeper configuration will use the internal pull resistor to keep the bus high If the last logic level on the pin bus was 0 the bus keeper will use the internal pull resistor to keep the bus...

Page 114: ...set as input Figure 11 7 Output configuration Wired AND with optional pull up 11 4 Reading the Pin Value Independent of the pin data direction the pin value can be read from the IN register as shown i...

Page 115: ...erted input configuration Input sensing can be used to trigger interrupt requests IREQ or events when there is a change on the pin The I O pins support synchronous and asynchronous input sensing Synch...

Page 116: ...ke up but no interrupt request will be generated A low level can always be detected by all pins regardless of a peripheral clock being present or not If a pin is configured for low level sensing the i...

Page 117: ...Port Functions Most port pins have alternate pin functions in addition to being a general purpose I O pin When an alternate function is enabled it might override the normal port pin function or pin v...

Page 118: ...peripheral clock and event channel 0 events to a pin This can be used to clock control and synchronize external functions and hardware to internal device tim ing The output port pin is selectable If...

Page 119: ...being written the same way during identical write operations 11 12 Virtual Ports Virtual port registers allow the port registers to be mapped virtually in the bit accessible I O memory space When this...

Page 120: ...e DIR register 11 13 3 DIRCLR Data Direction Clear register Bit 7 0 DIRCLR 7 0 Port Data Direction Clear This register can be used instead of a read modify write to set individual pins as input Writin...

Page 121: ...This register can be used instead of a read modify write to set the output value of individual pins to one Writing a one to a bit will set the corresponding bit in the OUT register Reading this reg i...

Page 122: ...Interrupt Control Register Bit 7 4 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bit 3...

Page 123: ...The INTnIF flag is set when a pin change state matches the pin s input sense configuration and the pin is set as source for port interrupt n Writing a one to this flag s bit location will clear the fl...

Page 124: ...0 Output Compare A Setting this bit will move the location of OC0A from Px0 to Px4 If this bit is set and PWM from both timer counter 0 and timer counter 1 is enabled the resulting PWM will be an OR m...

Page 125: ...y such as AC or ADC it is recommended to configure the pin to INPUT_DISABLE Table 11 4 Output pull configuration OPC 2 0 Group Configuration Description Output Configuration Pull Configuration 000 TOT...

Page 126: ...ers is equal to accessing the actual port registers See Table 11 6 for configuration Bit 3 0 VP0MAP Virtual Port 0 Mapping These bits decide which ports should be mapped to Virtual Port 0 The register...

Page 127: ...ently from those of EVOUT The port pin must be configured as output for the event to be available on the pin Table 11 6 Virtual port mapping VPnMAP 3 0 Group Configuration Description 0000 PORTA PORTA...

Page 128: ...vent Control register Bit 7 3 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Table 11 7...

Page 129: ...the available selections Table 11 10 Event channel output selection EVOUTSEL 2 0 Group Configuration Description 000 0 Event channel 0 output to pin 001 1 Event channel 1 output to pin 010 2 Event cha...

Page 130: ...register B When a port is mapped as virtual accessing this register is identical to accessing the actual OUT register for the port 11 15 3 IN Data Input Value Bit 7 0 IN 7 0 Data Input Value This regi...

Page 131: ...nd the pin is set as source for port interrupt n Writing a one to this flag s bit location will clear the flag For enabling and executing the interrupt refer to the interrupt level description The con...

Page 132: ...ISC 2 0 124 0x11 PIN1CTRL INVEN OPC 2 0 ISC 2 0 124 0x12 PIN2CTRL INVEN OPC 2 0 ISC 2 0 124 0x13 PIN3CTRL INVEN OPC 2 0 ISC 2 0 124 0x14 PIN4CTRL INVEN OPC 2 0 ISC 2 0 124 0x15 PIN5CTRL INVEN OPC 2 0...

Page 133: ...A D 11 19 Interrupt Vector Summary Ports Table 11 11 Port interrupt vectors and their word offset address Offset Source Interrupt Description 0x00 INT0_vect Port interrupt vector 0 offset 0x02 INT1_ve...

Page 134: ...iew Atmel AVR XMEGA devices have a set of flexible 16 bit timer counters TC Their capabilities include accurate program execution timing frequency and waveform generation and input cap ture with time...

Page 135: ...tions are used throughout the documentation In general the term timer is used when the timer counter clock control is handled by an internal source and the term counter is used when the clock control...

Page 136: ...ounter value is also compared to the CCx registers These comparisons can be used to generate interrupt requests generate events for the event system The waveform generator modes use these comparisons...

Page 137: ...nt system The event selection EVSEL and event action EVACT settings are used to trigger an event action from one or more events This is referred to as event action controlled operation of the counter...

Page 138: ...ering Both the CCx and CCxBUF registers are available as an I O register This allows initialization and bypassing of the buffer register and the double buffering function 12 6 Counter Operation Depend...

Page 139: ...rolled up down counting Event system controlled quadrature decode counting 12 6 3 32 bit Operation Two timer counters can be used together to enable 32 bit counter operation By using two timer counter...

Page 140: ...re channels to capture external events and give them a timestamp To use capture the counter must be set for normal operation Events are used to trigger the capture i e any events from the event system...

Page 141: ...the capture 12 7 1 Input Capture Selecting the input capture event action makes the enabled capture channel perform an input capture on an event The interrupt flags will be set and indicate that there...

Page 142: ...ve edge events from both input sources and the result will have no meaning 12 7 3 Pulse Width Capture Selecting the pulse width measure event action makes the enabled compare channel perform the input...

Page 143: ...w timestamp If a buffer overflow is detected the new value is rejected the error interrupt flag is set and the optional interrupt is generated 12 8 Compare Channel Each compare channel continuously co...

Page 144: ...y waveform generation The waveform frequency fFRQ is defined by the following equation where N represents the prescaler divider used The waveform generated will have a maximum frequency of half of the...

Page 145: ...ximum frequency of half of the peripheral clock frequency fclkPER when CCA is set to zero 0x0000 and no prescaling is used This also applies when using the hi res extension since this increases the re...

Page 146: ...peripheral clock frequency fclkPER when CCA is set to zero 0x0000 and no prescaling is used This also applies when using the hi res extension since this increases the resolution and not the frequency...

Page 147: ...vent gen eration and available events refer to Event System on page 45 12 10 Timer Counter Commands A set of commands can be given to the timer counter by software to immediately change the state of t...

Page 148: ...generation mode of operation will override the port output register for the corresponding OCn output pin When input capture operation is selected the CCxEN bits enable the capture operation for the c...

Page 149: ...TRLC Control register C Bit 7 4 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bit 3 0 C...

Page 150: ...carry propagation delay when cascading two counters via the event system Bit 3 0 EVSEL 3 0 Timer Event Source Select These bits select the event channel source for the timer counter For the selected e...

Page 151: ...None 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1nnn CHn Event channel n n 0 3 Bit 7 6 5 4 3 2 1 0 0x04 BYTEM 1 0 CTRLE Read Write R R R R R R R...

Page 152: ...ultilevel Interrupt Controller on page 101 12 11 8 CTRLFCLR CTRLFSET Control register F Clear Set This register is mapped into two I O memory locations one for clearing CTRLxCLR and one for setting th...

Page 153: ...CLR CTRLFSET Control register F Clear Set on page 152 for information on how to access this type of status register Bit 7 5 Reserved These bits are unused and reserved for future use For compatibility...

Page 154: ...FRQ or PWM waveform generation mode of operation ERRIF is set on a fault detect con dition from the fault protection feature in the AWeX extention For timer counters which do not have the AWeX extenti...

Page 155: ...the MSB of the 16 bit counter register 12 11 14 PERL Period register L The PERH and PERL register pair represents the 16 bit value PER PER contains the 16 bit TOP value in the timer counter Bit 7 0 P...

Page 156: ...occurs Bit 7 0 CCx 7 0 These bits hold the LSB of the 16 bit compare or capture register 12 11 17 CCxH Compare or Capture x register H Bit 7 0 CCx 15 8 These bits hold the MSB of the 16 bit compare or...

Page 157: ...ssing any of these registers using the CPU will affect the corresponding CCxBV status bit Bit 7 0 CCxBUF 7 0 These bits hold the LSB of the 16 bit compare or capture buffer register 12 11 21 CCxBUFH C...

Page 158: ...d 0x26 PERL PER 7 0 155 0x27 PERH PER 8 15 156 0x28 CCAL CCA 7 0 156 0x29 CCAH CCA 15 8 156 0x2A CCBL CCB 7 0 156 0x2B CCBH CCB 15 8 156 0x2C CCCL CCC 7 0 156 0x02D CCCH CCC 15 8 156 0x2E CCDL CCD 7 0...

Page 159: ...r must run from a non prescaled periph eral clock The timer counter will ignore its two least significant bits lsb in the counter and counts by four for each peripheral clock cycle Overflow underflow...

Page 160: ...hieved by operating at both edges of the peripheral 4x clock Bit 1 0 HREN 1 0 High Resolution Enable These bits enables the high resolution mode for a timer counter according to Table 13 1 Setting one...

Page 161: ...a functions to the timer counter in waveform generation WG modes It is primarily intended for use with different types of motor control and other power control applications It enables low and high sid...

Page 162: ...and override all the port pins When the pattern generator unit is enabled the DTI unit is bypassed The fault protection unit is connected to the event system enabling any event to trigger a fault con...

Page 163: ...he LS and HS never switch simultaneously OUT0 OUTOVEN0 CCAEN DTICCAEN INVEN0 OUT1 OUTOVEN1 CCBEN INVEN1 Px0 Px1 Channel A DTI LS HS OC0A OC0B OCALS OCAHS WG 0A WG 0B WG 0A CWCM OUT2 OUTOVEN2 CCCEN DTI...

Page 164: ...to their OFF state When a change is detected on the WG output the dead time counter is reloaded according to the edge of the input A positive edge initiates a counter reload of the DTLS register and a...

Page 165: ...tem can be used to trigger a fault action such as over current indication from analog comparator or ADC measurements When fault protection is enabled an incoming event from any of the selected event c...

Page 166: ...n be protected by writing the corresponding lock bit in the advanced waveform extension lock register For more details refer to I O Memory Protection on page 21 and AWEXLOCK Advanced Waveform Extensio...

Page 167: ...enerator for the corresponding CC channel This will override the timer counter waveform outputs 14 7 2 FDEMASK Fault Detect Event Mask register Bit 7 0 FDEVMASK 7 0 Fault Detect Event Mask These bits...

Page 168: ...longer active and the FDF has been cleared by software When both conditions are met the waveform output will return to normal operation at the next UPDATE condition In cycle by cycle mode the waveform...

Page 169: ...condition If this bit is zero no action will be taken The connected timer counter unit s lock update LUPD flag also affects the update for dead time buffers 14 7 5 DTBOTH Dead time Concurrent Write t...

Page 170: ...r register Bit 7 0 DTHSBUF Dead time High Side Buffer This register is the buffer for the DTHS register If double buffering is used valid content in this register is copied to the DTHS register on an...

Page 171: ...y Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 CTRL PGM CWCM DTICDAEN DTICCCEN DTICCBEN DTICCAEN 167 0x01 Reserved 0x02 FDEMASK FDEVMASK 7 0 167 0x03 FDCTRL FDDBD FDMODE FDAC...

Page 172: ...The faster 32 768kHz output can be selected if the RTC needs a resolution higher than 1ms The RTC can also be clocked from an external clock signal the 32 768kHz internal oscillator or the 32kHz inter...

Page 173: ...generate both interrupts and events The RTC will give a compare interrupt and or event at the first count after the counter value equals the Compare register value The RTC will give an overflow interr...

Page 174: ...bits define the prescaling factor for the RTC clock according to Table 15 1 on page 174 Bit 7 6 5 4 3 2 1 0 0x00 PRESCALER 2 0 CTRL Read Write R R R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table...

Page 175: ...ro when this register is written Bit 3 2 COMPINTLVL 1 0 Compare Match Interrupt Enable These bits enable the RTC compare match interrupt and select the interrupt level as described in Interrupts and P...

Page 176: ...s The low byte of the 16 bit register is stored here when it is written by the CPU The high byte of the 16 bit register is stored when the low byte is read by the CPU For more details refer to Accessi...

Page 177: ...ion between the RTC clock and system clock domains there is a latency of two RTC clock cycles from updating the register until this has an effect Application software needs to check that the SYNCBUSY...

Page 178: ...effect Application software needs to check that the SYNCBUSY flag in the STATUS Status register on page 175 is cleared before writing to this register If the COMP value is higher than the PER value n...

Page 179: ...VL 1 0 OVFINTLVL 1 0 175 0x03 INTFLAGS COMPIF OVFIF 176 0x04 TEMP TEMP 7 0 176 0x08 CNTL CNT 7 0 177 0x09 CNTH CNT 15 8 176 0x0A PERL PER 7 0 177 0x0B PERH PER 15 8 177 0x0C COMPL COMP 7 0 178 0x0D CO...

Page 180: ...e or several masters that can take control of the bus An arbitration process handles priority if more than one master tries to transmit data at the same time Mechanisms for resolving bus contention ar...

Page 181: ...to the bus and the master will use this to address a slave and initiate a data transaction Several masters can be connected to the same bus called a multi master environment An arbi tration mechanism...

Page 182: ...ns are used for marking the beginning START and end STOP of a transaction The master issues a START condition S by indicating a high to low transition on the SDA line while the SCL line is kept high T...

Page 183: ...address R W bit and acknowledge bit combined is the address packet Only one address packet for each START condition is allowed also when 10 bit addressing is used The R W bit specifies the direction...

Page 184: ...ddress the master can start receiving data from the slave There are no limitations to the number of data packets that can be transferred The slave transmits the data while the master signals ACK or NA...

Page 185: ...o vides time to process incoming or prepare outgoing data or perform other time critical tasks In the case where the slave is stretching the clock the master will be forced into a wait state until the...

Page 186: ...eriod it releases the SCL line However the SCL line will not go high until all masters have released it Consequently the SCL line will be held low by the device with the longest low period DEVICE2 Dev...

Page 187: ...hile in idle state the owner state is entered If the complete transaction was performed without interference i e no collisions are detected the master will issue a STOP condition and the bus state wil...

Page 188: ...g the START condition Depending on arbitration and the R W direction bit one of four distinct cases M1 to M4 arises following the address packet The different cases must be handled in software 16 5 1...

Page 189: ...repare new data to send During data transfer the master is continuously monitoring the bus for collisions The received acknowledge flag must be checked by software for each data packet transmitted bef...

Page 190: ...his can be read by software to determine the type of operation currently in progress Depending on the R W direction bit and bus condition one of four distinct cases S1 to S4 arises following the addre...

Page 191: ...t flag is set and the slave must indicate ACK or NACK After indicating a NACK the slave must expect a STOP or repeated START condition 16 6 3 Transmitting Data Packets The slave will know when an addr...

Page 192: ...it enables the use of the external driver interface and clearing this bit enables nor mal two wire mode See Table 16 2 on page 192 for details Bit 7 6 5 4 3 2 1 0 0x00 SDAHOLD 1 0 EDIEN CTRL Read Writ...

Page 193: ...3 ENABLE Enable TWI Master Setting the enable TWI master ENABLE bit enables the TWI master Bit 2 0 Reserved These bits are unused and reserved for future use For compatibility with future devices alwa...

Page 194: ...master s acknowledge behavior in master read mode The acknowledge action is executed when a command is written to the CMD bits If SMEN in the CTRLB register is set the acknowledge action is performed...

Page 195: ...Bit 6 WIF Write Interrupt Flag This flagis set when a byte is transmitted in master write mode The flag is set regardless of the occurrence of a bus error or an arbitration lost condition WIF is also...

Page 196: ...s Error This flag is set if an illegal bus condition has occurred An illegal bus condition occurs if a repeated START or a STOP condition is detected and the number of received or transmitted bits fro...

Page 197: ...ster read and no acknowledge is sent yet the acknowledge action is sent before the repeated START condition After completing the operation and the acknowledge bit from the slave is received the SCL li...

Page 198: ...n page 101 Bit 5 DIEN Data Interrupt Enable Setting the data interrupt enable DIEN bit enables the data interrupt when the data interrupt flag DIF in the STATUS register is set The INTLVL bits must be...

Page 199: ...ster is set the acknowledge action is performed when the DATA register is read Table 16 7 lists the acknowledge actions Bit 1 0 CMD 1 0 Command Writing these bits trigger the slave operation as define...

Page 200: ...bit in the CTRLA register is set a STOP condition on the bus will also set APIF Writing a one to this bit location will clear APIF When set for an address interrupt the slave forces the SCL line low...

Page 201: ...errors to be detected the bus state logic must be enabled This is done by enabling the TWI master Bit 1 DIR Read Write Direction The R W direction DIR flag reflects the direction bit from the last ad...

Page 202: ...data byte from the slave followed by the slave receiving the acknowledge bit from the master DIF and CLKHOLD are set When a master writes data to the slave DIF and CLKHOLD are set when one byte has be...

Page 203: ...Bit 0 ADDREN Address Enable By default this bit is zero and the ADDRMASK bits acts as an address mask to the ADDR reg ister If this bit is set to one the slave address match logic responds to the two...

Page 204: ...0 QCEN SMEN 193 0x02 CTRLC ACKACT CMD 1 0 194 0x03 STATUS RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE 1 0 195 0x04 BAUD BAUD 7 0 196 0x05 ADDR ADDR 7 0 197 0x06 DATA DATA 7 0 197 Address Name Bit 7...

Page 205: ...communication cycle by pulling the slave select SS signal low for the desired slave Master and slave prepare the data to be sent in their respective shift regis ters and the master generates the requ...

Page 206: ...is being driven low the SPI module will interpret this as another master trying to take control of the bus To avoid bus contention the master will take the following action 1 The master enters slave m...

Page 207: ...ading edge is the first clock edge of a clock cycle The trailing edge is the last clock edge of a clock cycle Figure 17 2 SPI transfer modes Bit 1 Bit 6 LSB MSB Mode 0 SAMPLE I MOSI MISO CHANGE 0 MOSI...

Page 208: ...These bits select the transfer mode The four combinations of SCK phase and polarity with respect to the serial data are shown in Table 17 2 on page 208 These bits decide whether the first edge of a c...

Page 209: ...mplete and one byte is completely shifted in out of the DATA register If SS is configured as input and is driven low when the SPI is in master mode this will also set this flag IF is cleared by hardwa...

Page 210: ...bility with future devices always write these bits to zero when this register is written 17 6 4 DATA Data register The DATA register is used for sending and receiving data Writing to the register init...

Page 211: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 CTRL CLK2X ENABLE DORD MASTER MODE 1 0 PRESCALER 1 0 208 0x01 INTCTRL INTLVL 1 0 209 0x02 STATUS IF WRCOL 209 0x03 DATA DATA 7 0 210 Table 17 4 SPI int...

Page 212: ...e Double buffered operation Configurable data order Operation up to 1 2 of the peripheral clock frequency IRCOM module for IrDA compliant pulse modulation demodulation 18 2 Overview The universal sync...

Page 213: ...chronous data reception It includes frame error buffer overflow and parity error detection When the USART is set in master SPI mode all USART specific logic is disabled leaving the transmit and receiv...

Page 214: ...d by the period setting BSEL an optional scale setting BSCALE and the peripheral clock frequency fPER Table 18 1 on page 215 contains equations for calculating the baud rate in bits per second and for...

Page 215: ...imum XCK clock speed must be reduced or the peripheral clock must be increased accordingly Table 18 1 Equations for calculating baud rate register settings Operating Mode Conditions Baud Rate 1 Calcul...

Page 216: ...he inverted I O INVEN setting for the corresponding XCK port pin the XCK clock edges used for data sampling and data change can be selected If inverted I O is disabled INVEN 0 data will be changed at...

Page 217: ...bits A frame starts with the start bit followed by all the data bits least significant bit first and most significant bit last If enabled the parity bit is inserted after the data bits before the fir...

Page 218: ...low 2 Set the TxD and optionally the XCK pin as output 3 Set the baud rate and frame format 4 Set the mode of operation enables XCK pin output in synchronous mode 5 Enable the transmitter or the recei...

Page 219: ...put automatically by hardware even if it was configured as out put by the user 18 7 Data Reception The USART Receiver When the receiver is enabled the RxD pin functions as the receiver s serial input...

Page 220: ...The clock recovery unit synchronizes the internal clock to the incoming serial frames Figure 18 6 on page 220 illustrates the sampling process for the start bit of an incoming frame The sample rate i...

Page 221: ...ter the last of the bits used for majority voting For normal speed mode the first low level sample can be at the point marked A in Stop Bit Sampling and Next Start Bit Sampling For double speed mode t...

Page 222: ...f the slowest incoming data rate that can be accepted in relation to the receiver baud rate Rfast The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate...

Page 223: ...baud rate generator works by doing uneven counting and then distrib uting the error evenly over the entire frame A typical count sequence for an ordinary baud rate generator is 2 1 0 2 1 0 2 1 0 2 wh...

Page 224: ...Disabling of the USART transmitter or receiver in master SPI mode is identical to their disabling in normal USART operation 18 11 USART SPI vs SPI The USART in master SPI mode is fully compatible wit...

Page 225: ...ignore the frames until another address frame is received 18 12 1 Using Multiprocessor Communication Mode The following procedure should be used to exchange data in multiprocessor communication mode...

Page 226: ...226 8210C AVR 09 11 Atmel AVR XMEGA D For devices with more than one USART IRCOM mode can be enabled for only one USART at a time For details refer to IRCOM IR Communication Module on page 234...

Page 227: ...status of the receive buffer 18 14 2 STATUS Status register Bit 7 RXCIF Receive Complete Interrupt Flag This flag is set when there are unread data in the receive buffer and cleared when the receive b...

Page 228: ...en writing the STATUS register This flag is not used in master SPI mode operation Bit 3 BUFOVF Buffer Overflow This flag indicates data loss due to a receiver buffer full condition This flag is set if...

Page 229: ...evel as described in Interrupts and Programmable Multilevel Interrupt Controller on page 101 The enabled interrupt will be triggered when the DREIF flag in the STATUS register is set 18 14 4 CTRLB Con...

Page 230: ...tailed information see Multipro cessor Communication Mode on page 225 This bit is unused in master SPI mode operation Bit 0 TXB8 Transmit Bit 8 TXB8 is the ninth data bit in the character to be transm...

Page 231: ...er of stop bits to be inserted by the transmitter according to Table 18 8 on page 231 The receiver ignores this setting This bit is unused in master SPI mode operation Bit 2 0 CHSIZE 2 0 Character Siz...

Page 232: ...ons by the transmitter and receiver will be corrupted if the baud rate is changed Writing BSEL will trigger an immediate update of the baud rate prescaler See the equations in Table 18 1 on page 215 1...

Page 233: ...CHSIZE 2 0 230 0x06 BAUDCTRLA BSEL 7 0 232 0x07 BAUDCTRLB BSCALE 3 0 BSEL 11 8 232 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 DATA DATA 7 0 227 0x01 STATUS RXCIF TXCIF DRE...

Page 234: ...SART to enable infrared pulse encod ing decoding for that USART Figure 19 1 IRCOM connection to USARTs and associated port pins The IRCOM is automatically enabled when a USART is set in IRCOM mode The...

Page 235: ...ulse was received The module can only be used in combination with one USART at a time Thus IRCOM mode must not be set for more than one USART at a time This must be ensured in the user software 19 2 1...

Page 236: ...L must be configured before the USART transmitter is enabled TXEN 19 3 2 RXPLCTRL Receiver Pulse Length Control Register Bit 7 0 RXPLCTRL 7 0 Receiver Pulse Length Control This 8 bit value sets the fi...

Page 237: ...m the USART s RX pin is automatically disabled 19 4 Register Summary Table 19 1 Event channel selection EVSEL 3 0 Group Configuration Event Source 0000 None 0001 Reserved 0010 Reserved 0011 Reserved 0...

Page 238: ...data stream or a block of data as input and generates a 16 or 32 bit output that can be appended to the data and used as a checksum When the same data are later received or read the device or applica...

Page 239: ...ource The CRC module operates on bytes only Figure 20 1 CRC generator block diagram 20 4 CRC on Flash memory A CRC 32 calculation can be performed on the entire flash memory on only the application se...

Page 240: ...to the CRC module using the CPU and writing the data to the DATAIN register Using this method an arbitrary number of bytes can be written to the register by the CPU and CRC is done continuously for ea...

Page 241: ...Source These bits select the input source for generating the CRC The selected source is locked until either the CRC generation is completed or the CRC module is reset CRC generation complete is gener...

Page 242: ...is selected and as long as the source is using the CRC module If the I O interface is selected as the source the flag can be cleared by writing a one this location If flash memory is selected as the s...

Page 243: ...he generated CRC 20 6 5 CHECKSUM1 Checksum Byte 1 Bit 7 0 CHECKSUM 15 8 These bits hold byte 1 of the generated CRC 20 6 6 CHECKSUM2 Checksum Byte 2 Bit 7 0 CHECKSUM 23 16 These bits hold byte 2 of th...

Page 244: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 CTRL RESET 1 0 CRC32 SOURCE 3 0 241 0x01 STATUS ZERO BUSY 242 0x02 Reserved 0x03 DATAIN DATAIN 7 0 242 0x04 CHECKSUM0 CHECKSUM 7 0 243 0x05 CHECKSUM1 CHE...

Page 245: ...ult 21 2 Overview The ADC converts analog signals to digital values The ADC has 12 bit resolution and is capable of converting up to 300 thousand samples per second MSPS The input selection is flexibl...

Page 246: ...fferential and so for single ended measurements the negative input is connected to a fixed internal value The four types of measurements and their corresponding input options are shown in Figure 21 2...

Page 247: ...plified by the gain stage before the result is converted The ADC must be in signed mode when differential input with gain is used The gain is selectable to 1 2x 1x 2x 4x 8x 16x 32x and 64x gain Figure...

Page 248: ...round The temperature sensor gives an output voltage that increases linearly with the internal temper ature of the device One or more calibration points are needed to compute the temperature from a me...

Page 249: ...nected to a fixed value given by the formula below which is half of the voltage reference VREF minus a fixed offset as it is for single ended unsigned input Refer to Figure 21 11 on page 251 for detai...

Page 250: ...will be in the range 0 to 4095 0x0 0x0FFF The ADC transfer functions can be written as VINP is the single ended or internal input The ADC can be configured to generate either an 8 bit or a 12 bit resu...

Page 251: ...11 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1111 1000 0000 0011 1111 1000 0000 0010 1111 1000 0000 0001 1111 1000 0000 0000 16 bit result reg...

Page 252: ...C that matches the application requirements and is within the operating range of the ADC Figure 21 12 ADC prescaler The maximum ADC sample rate is given by the he ADC clock frequency fADC The ADC can...

Page 253: ...ure 21 14 ADC timing for one single conversion with increased sampling time SAMPVAL 6 21 9 2 Single Conversion with Gain Figure 21 15 on page 254 to Figure 21 17 on page 255 show the ADC timing for on...

Page 254: ...n CONVERTING BIT START IF ADC SAMPLE AMPLIFY msb 10 9 8 7 6 5 4 3 2 1 lsb clkADC 1 2 3 4 5 6 7 8 9 CONVERTING BIT IF ADC SAMPLE AMPLIFY msb 10 9 8 7 6 5 4 3 2 1 lsb GAINSTAGE SAMPLE CONVERTING BIT STA...

Page 255: ...acitor Figure 21 18 on page 255 and Figure 21 19 on page 255 show the ADC input channels Figure 21 18 ADC input for single ended measurements Figure 21 19 ADC input for differential measurements and d...

Page 256: ...oftware 21 13 Synchronous Sampling Starting an ADC conversion can cause an unknown delay between the start trigger or event and the actual conversion since the peripheral clock is faster than the ADC...

Page 257: ...will resume where it left off i e if any conver sions were pending these will enter the ADC and complete Bit 0 ENABLE Enable Setting this bit enables the ADC 21 14 2 CTRLB ADC Control register B Bit...

Page 258: ...This bit is unused and reserved for future use For compatibility with future devices always write this bit to zero when this register is written 21 14 3 REFCTRL Reference Control register Bit 7 Reser...

Page 259: ...21 14 4 EVCTRL Event Control register Bit 7 5 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is wri...

Page 260: ...n page 260 Table 21 4 ADC event channel select EVSEL 1 0 Group Configuration Selected Event Lines 00 0 Event channel 0 selected inputs 01 1 Event channel 1 selected inputs 10 2 Event channel 2 selecte...

Page 261: ...egister is stored here when the low byte is read by the CPU This register can also be read and written from the user software For more details on 16 bit register access refer to Accessing 16 bit Regis...

Page 262: ...e 12 bit ADC result 21 14 10 2 12 bit Mode Right Adjusted Bit 7 4 Reserved These bits will in practice be the extension of the sign bit CHRES11 when the ADC works in dif ferential mode and set to zero...

Page 263: ...eading and writing 16 bit registers refer to Accessing 16 bit Registers on page 11 Bit 7 0 CMP 15 0 Compare Value High These are the eight msbs of the 16 bit ADC compare value In signed mode the numbe...

Page 264: ...0 Gain Factor These bits define the gain factor for the ADC gain stage See Table 21 5 on page 260 Gain is valid only with certain MUX settings See MUXCTRL MUX Control registers on page 265 Bit 1 0 INP...

Page 265: ...positive input signal 01 SINGLEENDED Single ended positive input signal 10 DIFF Differential input signal 11 DIFFWGAIN Differential input signal with gain Bit 7 6 5 4 3 2 1 0 0x01 MUXPOS 3 0 MUXNEG 2...

Page 266: ...9 ADC9 pin 1010 PIN10 ADC10 pin 1011 PIN11 ADC11 pin 1100 PIN12 ADC12 pin 1101 PIN13 ADC13 pin 1110 PIN14 ADC14 pin 1111 PIN15 ADC15 pin Table 21 12 ADC MUXNEG configuration INPUTMODE 1 0 10 different...

Page 267: ...s Bit 7 1 Reserved These bits are unused and reserved for future use For compatibility with future devices always write these bits to zero when this register is written Bit 0 IF Interrupt Flag The int...

Page 268: ...t Mode Right Adjusted Bit 7 4 Reserved These bits will in practice be the extension of the sign bit CHRES11 when the ADC works in dif ferential mode and set to zero when the ADC works in signed mode B...

Page 269: ...register contains the offset for the next input source to be converted on ADC channel 0 CH0 The actual MUX setting for positive input equals MUXPOS OFFSET The value is incremented after each conversi...

Page 270: ...erved 0x0A Reserved 0x0B Reserved 0x0C CALL CAL 7 0 261 0x0D CALH CAL 11 8 0x0E Reserved 0x0F Reserved 0x10 CH0RESL CH0RES 7 0 263 0x11 CH0RESH CH0RES 15 8 262 0x12 Reserved 0x13 Reserved 0x14 Reserve...

Page 271: ...sts and or events upon several different combinations of input change Two important properties of the analog comparator s dynamic behavior are hysteresis and prop agation delay Both of these parameter...

Page 272: ...ap reference voltage Voltage scaler which provides a 64 level scaling of the internal VCC voltage 22 4 Signal Compare In order to start a signal comparison the analog comparator must be configured wit...

Page 273: ...ned and the analog comparators give information about whether an input signal is within this range or not Figure 22 2 The Analog comparators in window mode 22 7 Input Hysteresis Application software c...

Page 274: ...n this register is written Bit 2 1 HYSMODE 1 0 Hysteresis Mode Select These bits select the hysteresis mode according to Table 22 2 For details on actual hysteresis levels refer to the device datashee...

Page 275: ...ich input will be connected to the negative input of analog comparator n according to Table 22 4 on page 275 Bit 7 6 5 4 3 2 1 0 0x02 0x03 MUXPOS 2 0 MUXNEG 2 0 ACnMUXCTRL Read Write R R R W R W R W R...

Page 276: ...r is written Bit 5 0 SCALEFAC 5 0 Voltage Scaling Factor These bits define the scaling factor for the Vcc voltage scaler The input to the analog compara tor VSCALE is 22 8 5 WINCTRL Window Function Co...

Page 277: ...ows the current state of the output signal fromAC0 Bit 3 Reserved This bit is unused and reserved for future use For compatibility with future devices always write this bit to zero when this register...

Page 278: ...s bit location 22 8 7 CURRCTRL Current Source Control register Bit 7 CURRENT Current Source Enable Setting this bit to one will enable the constant current source Bit 6 CURRMODE Current Mode Setting t...

Page 279: ...write these bits to zero when this register is written Bit 3 0 CALIB 3 0 Current Source Calibration The constant current source is calibrated during production A calibration value can be read from the...

Page 280: ...MUXCTRL MUXPOS 2 0 MUXNEG 2 0 275 0x04 CTRLA AC1OUT ACOOUT 276 0x05 CTRLB SCALEFAC5 0 276 0x06 WINCTRL WEN WINTMODE 1 0 WINTLVL 1 0 276 0x07 STATUS WSTATE 1 0 AC1STATE AC0STATE WIF AC1IF AC0IF 277 0x0...

Page 281: ...and Debug Interface PDI is an Atmel proprietary interface for external program ming and on chip debugging of a device The PDI supports fast programming of nonvolatile memory NVM spaces flash EEPOM fu...

Page 282: ...debugger and the device Figure 23 2 on page 282 shows a typical connection Figure 23 2 PDI connection The remainder of this section is intended for use only by third parties developing programmers or...

Page 283: ...vity on the clock line This will automatically disable the PDI If not disabled by a fuse the reset function of the Reset PDI_CLK pin is enabled again This also means that the minimum pro gramming freq...

Page 284: ...smitter simply shifts out the start bit data bits parity bit and the two stop bits on the PDI_DATA line The transmission speed is dictated by the PDI_CLK signal While in transmission mode IDLE bits hi...

Page 285: ...rammer will loose control of the PDI_DATA line at the point where the PDI changes from RX to TX mode The guard time relaxes this critical phase of the communication When the programmer changes from RX...

Page 286: ...DI_DATA line How ever the two stop bits should always be transmitted as ones within a single frame enabling collision detection at least once per frame 23 4 PDI Controller The PDI controller performs...

Page 287: ...g There are several situations that are considered exceptions from normal operation The excep tions depend on whether the PDI is in RX or TX mode While the PDI is in RX mode the exceptions are PDI The...

Page 288: ...ace into the physical layer shift register for serial read out The LD instruction is based on indirect addressing pointer access which means that the address must be stored in the pointer register pri...

Page 289: ...sed to store count values that are serially shifted into the physical layer shift register to the repeat counter register The instruction that is loaded directly after the REPEAT instruction operand s...

Page 290: ...Pointer Register The pointer register is used to store an address value that specifies locations within the PDIBUS address space During direct data access the pointer register is updated by the specif...

Page 291: ...ster space CSRS space 23 5 3 Repeat Counter Register The REPEAT instruction is always accompanied by one or more operand bytes that define the number of times the next instruction should be repeated T...

Page 292: ...for future use For compatibility with future devices always write this bit to zero when this register is written 23 6 2 RESET Reset register Bit 7 0 RESET 7 0 Reset Signature When the reset signature...

Page 293: ...Table 23 1 on page 293 In order to speed up the communica tion the guard time should be set to the lowest safe configuration accepted No guard time is inserted when switching from TX to RX mode 23 7...

Page 294: ...r to Memories on page 17 The NVM can be accessed for read and write from application software through self program ming and from an external programmer Accessing the NVM is done through the NVM contro...

Page 295: ...of commands 24 4 1 Action triggered Commands Action triggered commands are triggered when the command execute CMDEX bit in the NVM control register A CTRLA is written Action triggered commands typica...

Page 296: ...is filled one word at a time and it must be erased before it can be loaded When loading the page buffer with new content the result is a binary AND between the existing content of the page buffer loc...

Page 297: ...ernative 2 Fill the flash page buffer Perform an atomic page erase and write Alternative 3 fill the buffer after a page erase Perform a flash page erase Fill the flash page bufferPerform a flash page...

Page 298: ...he power is sufficient again in case the write sequence failed or only partly succeeded 24 10 CRC Functionality It is possible to run an automatic cyclic redundancy check CRC on the flash program memo...

Page 299: ...d organized in pages the Z pointer can be treated as having two sections The least significant bits address the words within a page while the most signifi cant bits address the page within the flash T...

Page 300: ...ection register on page 13 CCP is not required for external programming The two last columns show the address pointer used for addressing and the source destination data register Section 24 11 1 1 on...

Page 301: ...TUS will be set until the page buffer is erased 0x02E WRITE_FLASH_PAGE Write flash page SPM N Y 2 Y Y Z pointer 0x2F ERASE_WRITE_FLASH_PAGE Erase and write flash page SPM N Y 2 Y Y Z pointer 0x3A FLAS...

Page 302: ...t as long the flash is busy and the application section can not be accessed 24 11 2 5 Write Flash Page The write flash page command is used to write the flash page buffer into one flash page in the fl...

Page 303: ...set until the erase operation is finished The FBUSY flag is set as long the flash is busy and the application section cannot be accessed 24 11 2 9 Application Section Boot Loader Section Page Write T...

Page 304: ...er This requires the timed CCP sequence during self programming The BUSY flag in the NVM STATUS register will be set and the CPU is halted during the execu tion of the CRC command The CRC checksum wil...

Page 305: ...ce destination data register Section 24 11 3 1 on page 305 through Section 24 11 3 2 on page 305 explain in detail the algo rithm for each NVM operation 24 11 3 1 Write Lock Bits The write lock bits c...

Page 306: ...EPROM through the NVM controller the NVM address ADDR register is used to address the EEPROM while the NVM data DATA register is used to store or load EEPROM data For EEPROM page programming the ADDR...

Page 307: ...guration change protection CCP during self programming or not CCP is not required for external pro gramming The last two columns show the address pointer used for addressing and the source destination...

Page 308: ...M Only the locations that are loaded and tagged in the EEPROM page buffer will be written 1 Load the NVM CMD register with the write EEPROM page command 2 Load the NVM ADDR register with the address o...

Page 309: ...rogramming is the method for programming code and nonvolatile data into the device from an external programmer or debugger This can be done by both in system or in mass pro duction programming For ext...

Page 310: ...interface is enabled and active from the PDI 24 12 2 NVM Programming When the PDI NVM interface is enabled all memories in the device are memory mapped in the PDI address space The PDI controller doe...

Page 311: ...ng For external programming the trigger for action triggered commands is to set the CMDEX bit in the NVM CTRLA register CMDEX The read triggered commands are triggered by a direct or indirect load ins...

Page 312: ...finished 24 12 3 2 Read NVM The read NVM command is used to read the flash EEPROM fuses and signature and calibra tion row sections 0x38 Application section CRC CMDEX Y Y Boot Loader Section 0x68 Eras...

Page 313: ...e write operation the low byte of the word location must be written before the high byte The low byte is then written into the temporary reg ister The PDI then writes the high byte of the word locatio...

Page 314: ...amming 1 Load the NVM CMD register with application boot loader section CRC command 2 Set the CMDEX bit in the NVM CTRLA register This requires the timed CCP sequence during self programming The BUSY...

Page 315: ...of the NVM controller Refer to Register Description PDI Control and Status Registers on page 292 for a complete register description of the PDI 24 14 Register Summary Refer to Register Description NVM...

Page 316: ...r 141 0x00B0 PORTCFG Port Configuration 162 0x0180 EVSYS Event System 80 0x01C0 NVM Non Volatile Memory NVM Controller 50 0x0200 ADCA Analog to Digital Converter on port A 381 0x0380 ACA Analog Compar...

Page 317: ...et Bit s in Register Rd Rd v K Z N V S 1 CBR Rd K Clear Bit s in Register Rd Rd FFh K Z N V S 1 INC Rd Increment Rd Rd 1 Z N V S 1 DEC Rd Decrement Rd Rd 1 Z N V S 1 TST Rd Test for Zero or Minus Rd R...

Page 318: ...then PC PC k 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC k 1 None 1 2 BRPL k Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC PC k 1 Non...

Page 319: ...Store Indirect and Post Increment Z Z Rr Z 1 None 1 1 ST Z Rr Store Indirect and Pre Decrement Z Z 1 None 2 1 STD Z q Rr Store Indirect with Displacement Z q Rr None 2 1 LPM Load Program Memory R0 Z...

Page 320: ...I A b Set Bit in I O Register I O A b 1 None 1 CBI A b Clear Bit in I O Register I O A b 0 None 1 BST Rr b Bit Store from Register to T T Rr b T 1 BLD Rd b Bit load from T to Register Rd b T None 1 SE...

Page 321: ...eferring revisions in this section are referring to the document revision 27 1 8210C 09 11 27 2 8210B 04 10 27 3 8210A 08 09 1 Updated all chapters and new figures added according the XMEGA AU manual...

Page 322: ...on Execution Timing 7 3 7 Status Register 8 3 8 Stack and Stack Pointer 8 3 9 Register File 9 3 10 RAMP and Extended Indirect Registers 10 3 11 Accessing 16 bit Registers 11 3 12 Configuration Change...

Page 323: ...mmary MCU Control 44 4 22 Interrupt Vector Summary NVM Controller 44 5 Event System 45 5 1 Features 45 5 2 Overview 45 5 3 Events 46 5 4 Event Routing Network 48 5 5 Event Timing 50 5 6 Filtering 50 5...

Page 324: ...ster Summary Sleep 86 7 9 Register Summary Power Reduction 86 8 Reset System 87 8 1 Features 87 8 2 Overview 87 8 3 Reset Sequence 88 8 4 Reset Sources 89 8 5 Register Description 93 8 6 Register Summ...

Page 325: ...11 Multi pin configuration 119 11 12 Virtual Ports 119 11 13 Register Descriptions Ports 120 11 14 Register Descriptions Port Configuration 126 11 15 Register Descriptions Virtual Port 130 11 16 Regis...

Page 326: ...14 6 Fault Protection 165 14 7 Register Description 167 14 8 Register Summary 171 15 RTC Real Time Counter 172 15 1 Features 172 15 2 Overview 172 15 3 Register Descriptions 174 15 4 Register Summary...

Page 327: ...eneration 214 18 4 Frame Formats 217 18 5 USART Initialization 218 18 6 Data Transmission The USART Transmitter 218 18 7 Data Reception The USART Receiver 219 18 8 Asynchronous Data Reception 220 18 9...

Page 328: ...7 Compare Function 251 21 8 Starting a Conversion 252 21 9 ADC Clock and Conversion Timing 252 21 10 ADC Input Model 255 21 11 Interrupts and Events 256 21 12 Calibration 256 21 13 Synchronous Sampli...

Page 329: ...tures 294 24 2 Overview 294 24 3 NVM Controller 295 24 4 NVM Commands 295 24 5 NVM Controller Busy Status 295 24 6 Flash and EEPROM Page Buffers 296 24 7 Flash and EEPROM Programming Sequences 297 24...

Page 330: ...T FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS I...

Page 331: ...Information Atmel ATXMEGA16D4 CU ATXMEGA16D4 MH ATXMEGA32D4 CU ATXMEGA32D4 MH ATXMEGA128D3 AUR ATXMEGA128D3 MHR ATXMEGA16D4 AUR ATXMEGA16D4 CUR ATXMEGA192D3 AUR ATXMEGA192D3 MHR ATXMEGA256D3 AUR ATXM...

Reviews:

No comments