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8210C–AVR–09/11
Atmel AVR XMEGA D
21.8
Starting a Conversion
Before a conversion is started, the input source must be selected. An ADC conversion can be
started either by the application software writing to the start conversion bit or from any events in
the event system.
21.8.1
Input Source Scan
It is possible to select a range of consecutive input sources that is automatically scanned and
measured when a conversion is started. This is done by setting the first (lowest) positive ADC
channel input using the MUX control register, and a number of consecutive positive input
sources. When a conversion is started, the first selected input source is measured and con-
verted, then the positive input source selection is incremented after each conversion until it
reaches the specified number of sources to scan.
21.9
ADC Clock and Conversion Timing
The ADC is clocked from the peripheral clock. The ADC can prescale the peripheral clock to pro-
vide an ADC Clock (clk
ADC
) that matches the application requirements and is within the
operating range of the ADC.
Figure 21-12.
ADC prescaler.
The maximum ADC sample rate is given by the he ADC clock frequency (f
ADC
). The ADC can
sample a new measurement on every ADC clock cycle.
The propagation delay of an ADC measurement is given by:
RESOLUTION is the resolution, 8 or 12 bits. The propagation delay will increase by one extra
ADC clock cycle if the gain stage (GAIN) is used.
The propagation delay is longer than one ADC clock cycle, but the pipelined design means that
the sample rate is limited not by the propagation delay, but by the ADC clock rate.
The most-significant bit (msb) of the result is converted first, and the rest of the bits are con-
verted during the next three (for 8-bit results) or five (for 12-bit results) ADC clock cycles.
Converting one bit takes a half ADC clock period. During the last cycle, the result is prepared
before the interrupt flag is set and the result is available in the result register for readout.
9-bit ADC Prescaler
Clk
ADC
PRESCALER[2:0]
CL
K/4
CL
K/8
CL
K/1
6
CL
K/3
2
CL
K/6
4
CL
K/1
2
8
Clk
PER
CL
K/2
5
6
CL
K/5
1
2
Sample Rate
f
ADC
=
Propagation Delay =
1
RESOLUTION
2
---------------------------------------
GAIN
+
+
f
ADC
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