55
8210C–AVR–09/11
Atmel AVR XMEGA D
• Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data
event will be enabled.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
• Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
• Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event
channel only when the event source has been active and sampled with the same level for the
number of peripheral clock cycles defined by DIGFILT.
5.8.3
STROBE – Strobe register
If the STROBE register location is written, each event channel will be set according to the
STROBE[n] and corresponding DATA[n] bit settings, if any are unequal to zero.
A single event lasting for one peripheral clock cycle will be generated.
Table 5-4.
QDIRM bit settings.
QDIRM[1:0]
Index Recognition State
0
0
{QDPH0, QDPH90} = 0b00
0
1
{QDPH0, QDPH90} = 0b01
1
0
{QDPH0, QDPH90} = 0b10
1
1
{QDPH0, QDPH90} = 0b11
Table 5-5.
Digital filter coefficient values .
DIGFILT[2:0]
Group Configuration
Description
000
1SAMPLE
One sample
001
2SAMPLES
Two samples
010
3SAMPLES
Three samples
011
4SAMPLES
Four samples
100
5SAMPLES
Five samples
101
6SAMPLES
Six samples
110
7SAMPLES
Seven samples
111
8SAMPLES
Eight samples
Bit
7
6
5
4
3
2
1
0
STROBE[7:0]
STROBE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0