102
8210C–AVR–09/11
Atmel AVR XMEGA D
10.3
Operation
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting
the global interrupt enable ( I ) bit in the CPU status register. The I bit will not be cleared when an
interrupt is acknowledged. Each interrupt level must also be enabled before interrupts with the
corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the
interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the
interrupt is either acknowledged or kept pending until it has priority. When the interrupt request
is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt
vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before
the interrupt occurred. One instruction is always executed before any pending interrupt is
served.
The PMIC status register contains state information that ensures that the PMIC returns to the
correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an
interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-
ing the interrupt. The status register (SREG) is not saved automatically upon an interrupt
request. The RET (subroutine return) instruction cannot be used when returning from the inter-
rupt handler routine, as this will not return the PMIC to its correct state.
10.4
Interrupts
All interrupts and the reset vector each have a separate program vector address in the program
memory space. The lowest address in the program memory space is the reset vector. All inter-
rupts are assigned individual control bits for enabling and setting the interrupt level, and this is
set in the control registers for each peripheral that can generate interrupts. Details on each inter-
rupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated with it. When the interrupt condition is present,
the interrupt flag will be set, even if the corresponding interrupt is not enabled. For most inter-
rupts, the interrupt flag is automatically cleared when executing the interrupt vector. Writing a
logical one to the interrupt flag will also clear the flag. Some interrupt flags are not cleared when
executing the interrupt vector, and some are cleared automatically when an associated register
is accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the
interrupt flag will be set and remembered until the interrupt has priority. If an interrupt condition
occurs while the corresponding interrupt is not enabled, the interrupt flag will be set and remem-
bered until the interrupt is enabled or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then
executed according to their order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock
bits are programmed. This feature improves software security. Refer to
for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration
change protection register is written with the correct signature. Refer to
for more details.