Atmel AVR XMEGA D Series, Manual, Page: 204 / 331

204
8210C–AVR–09/11
Atmel AVR XMEGA D
16.11 Register Summary - TWI
16.12 Register Summary - TWI Master
16.13 Register Summary - TWI Slave
16.14 Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – – – – – SDAHOLD EDIEN 192
+0x01 MASTER Offset address for TWI Master
+0x08 SLAVE Offset address for TWI Slave
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] RIEN WIEN ENABLE – – – 193
+0x01 CTRLB – – – – TIMEOUT[1:0] QCEN SMEN 193
+0x02 CTRLC – – – – – ACKACT CMD[1:0] 194
+0x03 STATUS RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0] 195
+0x04 BAUD BAUD[7:0] 196
+0x05 ADDR ADDR[7:0] 197
+0x06 DATA DATA[7:0] 197
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] DIEN APIEN ENABLE PIEN TPMEN SMEN 198
+0x01 CTRLB – – – – – ACKACT CMD[1:0] 199
+0x02 STATUS DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP 200
+0x03 ADDR ADDR[7:0] 201
+0x04 DATA DATA[7:0] 202
+0x05 ADDRMASK ADDRMASK[7:1] ADDREN 202
Table 16-10. TWI interrupt vectors and their word offset addresses.
Offset Source Interrupt Description
0x00 SLAVE_vect TWI slave interrupt vector
0x02 MASTER_vect TWI master interrupt vector