Atmel AVR XMEGA D Series, Manual, Page: 260 / 331

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8210C–AVR–09/11
Atmel AVR XMEGA D
• Bit 2:0 – EVACT[2:0]: Event Mode
These bits select and limit how many of the selected event input channel are used, and also fur-
ther limit the ADC channels triggers. They also define more special event triggers as defined in
Table 21-4 on page 260 .
21.14.5 PRESCALER – Clock Prescaler register
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2:0 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 21-6 on page
260 .
Table 21-4. ADC event channel select.
EVSEL[1:0] Group Configuration Selected Event Lines
00 0 Event channel 0 selected inputs
01 1 Event channel 1 selected inputs
10 2 Event channel 2 selected inputs
11 3 Event channel 3 selected inputs
Table 21-5. ADC event mode select.
EVACT[2:0] Group Configuration Event Input Operation Mode
000 NONE No event inputs
001 CH0 Event channel with the lowest number defined by
EVSEL triggers conversion on ADC channel 0
010 – Reserved
011 – Reserved
100 – Reserved
101 – Reserved
110 SYNCSWEEP The ADC is flushed and restarted for accurate timing
111 – Reserved
Bit 7 6 5 4 3 2 1 0
+0x04 – – – – – PRESCALER[2:0] PRESCALER
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 21-6. ADC prescaler settings .
PRESCALER[2:0] Group Configuration Peripheral Clock Division Factor
000 DIV4 4
001 DIV8 8