257
8210C–AVR–09/11
Atmel AVR XMEGA D
21.14 Register Description
–
ADC
21.14.1
CTRLA – Control register A
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – CH0START: Channel Start Single Conversion
Setting this bit will start an ADC conversion. Bit is cleared by hardware when the conversion has
started. Writing this bit is equivalent to writing the START bits inside the ADC channel register.
• Bit 1 – FLUSH: Pipeline Flush
Setting this bit will flush the ADC. When this is done, the ADC clock is restarted on the next
peripheral clock edge, and all conversions in progress are aborted and lost.
After the flush and the ADC clock restart, the ADC will resume where it left off; i.e., if any conver-
sions were pending, these will enter the ADC and complete.
• Bit 0 – ENABLE: Enable
Setting this bit enables the ADC.
21.14.2
CTRLB – ADC Control register B
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:5 – CURRLIMIT[1:0]: Current Limitation
These bits can be used to limit the current consumption of the ADC by reducing the maximum
ADC sample rate. The available settings are shown in
. The indicated
current limitations are nominal values. Refer to the device datasheet for actual current limitation
for each setting.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
CH0START
FLUSH
ENABLE
CTRLA
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
CURRLIMIT[1:0]
CONVMODE
FREERUN
RESOLUTION[1:0]
–
CTRLB
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0