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8210C–AVR–09/11
Atmel AVR XMEGA D
20.6.2
STATUS – Status register
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – ZERO: Checksum Zero
This flag is set if the CHECKSUM is zero when the CRC generation is complete. It is automati-
cally cleared when a new CRC source is selected.
When running CRC-32 and appending the checksum at the end of the packet (as little endian),
the final checksum shold be 0x2144df1c, and not zero. However, if the checksum is comple-
mented before it is appended (as little endian) to the data, the final result in the checksum
register will be zero.
See the description of CHECKSUM to read out different versions of the CHECKSUM.
• Bit 0 – BUSY: Busy
This flag is read as one when a source configuration is selected and as long as the source is
using the CRC module. If the I/O interface is selected as the source, the flag can be cleared by
writing a one this location. If flash memory is selected as the source, the flag is cleared when the
CRC generation is completed.
20.6.3
DATAIN – Data Input Register
• Bit 7:0 – DATAIN[7:0]
This register is used to store the data for which the CRC checksum is computed
. A new CHECK-
SUM is ready one clock cycle after the DATAIN register is written.
20.6.4
CHECKSUM0 – Checksum Byte 0
CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit
CHECKSUM value and the generated CRC. The registers are reset to zero by default, but it is
0110
—
Reserved for future use
0111
—
Reserved for future use
1xxx
—
Reserved for future use
Table 20-2.
CRC source select (Continued).
SOURCE[3:0]
Group configuration
Description
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
–
–
ZERO
BUSY
STATUS
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
+0x03
DATAIN[7:0]
DATAIN
Read/Write
W
W
W
W
W
W
W
W
Initial Value
0
0
0
0
0
0
0
0