11
8210C–AVR–09/11
Atmel AVR XMEGA D
3.11
Accessing 16-bit Registers
The
AVR
data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations.
These registers must be byte-accessed using two read or write operations. 16-bit registers are
connected to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The
low byte is then written into the temporary register. When the high byte of the 16-bit register is
written, the temporary register is copied into the low byte of the 16-bit register in the same clock
cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When
the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the
temporary register in the same clock cycle as the low byte is read. When the high byte is read, it
is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously
when reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-
bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be dis-
abled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
3.11.1
Accessing 24- and 32-bit Registers
For 24- and 32-bit registers, the read and write access is done in the same way as described for
16-bit registers, except there are two temporary registers for 24-bit registers and three for 32-bit
registers. The least-significant byte must be written first when doing a write, and read first when
doing a read.
3.12
Configuration Change Protection
System critical I/O register settings are protected from accidental modification. The SPM instruc-
tion is protected from accidental execution, and the LPM instruction is protected when reading
the fuses and signature row. This is handled globally by the configuration change protection
(CCP) register. Changes to the protected I/O registers or bits, or execution of protected instruc-
tions, are only possible after the CPU writes a signature to the CCP register. The different
signatures are described in the register description.
There are two modes of operation: one for protected I/O registers, and one for the protected
instructions, SPM/LPM.
3.12.1
Sequence for write operation to protected I/O registers
1.
The application code writes the signature that enable change of protected I/O registers
to the CCP register.
2.
Within four instruction cycles, the application code must write the appropriate data to
the protected register. Most protected registers also contain a write enable/change
enable bit. This bit must be written to one in the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to
the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed.