255
8210C–AVR–09/11
Atmel AVR XMEGA D
Figure 21-17.
ADC timing for one single conversion with 64x gain.
21.10 ADC Input Model
The voltage input must charge the sample and hold (S/H) capacitor in the ADC in order to
achieve maximum accuracy. Seen externally, the ADC input consists of an input channel
(R
channel
) and switch (R
switch
) resistance and the S/H capacitor.
show the ADC input channels.
Figure 21-18.
ADC input for single-ended measurements.
Figure 21-19.
ADC input for differential measurements and differential measurements with gain.
CONVERTING BIT
START
IF
ADC SAMPLE
AMPLIFY
msb
10
9
8
7
6
5
4
3
2
1
lsb
clk
ADC
1
2
3
4
5
6
7
8
9
10
CONVERTING BIT
IF
ADC SAMPLE
AMPLIFY
msb
10
9
8
7
6
5
4
3
2
1
lsb
GAINSTAGE SAMPLE
R
channel
R
switch
C
Sample
VCC/2
Positive
input
R
channel
R
switch
C
Sample
VCC/2
Positive
input
R
channel
R
switch
C
Sample
Negative
input