85
4317I–AVR–01/08
AT90PWM2/3/2B/3B
Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PB6). The selection
is made thanks to ICPSEL1 bit as described in
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Table 13-1.
ICPSEL1
ICPSEL1
Description
0
Select ICP1A as trigger for timer 1 input capture
1
Select ICP1B as trigger for timer 1 input capture
