309
4317I–AVR–01/08
AT90PWM2/3/2B/3B
Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements
Note:
1. ggThe timing requirements shown in
(i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
reading operation.
XTAL1
OE
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
Table 26-6.
Parallel Programming Characteristics, V
CC
= 5V ± 10%
Symbol
Parameter
Min.
Typ.
Max.
Units
V
PP
Programming Enable Voltage
11.5
12.5
V
I
PP
Programming Enable Current
250
μ
A
t
DVXH
Data and Control Valid before XTAL1 High
67
ns
t
XLXH
XTAL1 Low to XTAL1 High
200
ns
t
XHXL
XTAL1 Pulse Width High
150
ns
t
XLDX
Data and Control Hold after XTAL1 Low
67
ns
t
XLWL
XTAL1 Low to WR Low
0
ns
t
XLPH
XTAL1 Low to PAGEL high
0
ns
t
PLXH
PAGEL low to XTAL1 high
150
ns
t
BVPH
BS1 Valid before PAGEL High
67
ns
t
PHPL
PAGEL Pulse Width High
150
ns
t
PLBX
BS1 Hold after PAGEL Low
67
ns
t
WLBX
BS2/1 Hold after WR Low
67
ns
t
PLWL
PAGEL Low to WR Low
67
ns
t
BVWL
BS1 Valid to WR Low
67
ns
t
WLWH
WR Pulse Width Low
150
ns
t
WLRL
WR Low to RDY/BSY Low
0
1
μ
s
t
WLRH
WR Low to RDY/BSY High
3.7
5
ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
7.5
10
ms
