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Analog Devices adsp-2100, Manual

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13 Hardware Examples

13 – 6

Figure 13.2 shows an industry standard 

µ

-law companding codec

connected to a serial port (in this case, SPORT0) on an ADSP-21xx
processor. The codec’s analog input at VFXI+ is internally amplified by a
gain which is controlled by the resistor combination at GSX and VFXI–.
The gain is

20 

x

 log (R1 + R2)/R2

in this case, 20 log 2.

The ADSP-21xx controls codec operation by supplying master and bit
clock signals. In the configuration shown, the codec transmit and receive
sections operate synchronously. MCLKR and MCLKX are the master
clocks for the receive and transmit sections of the codec, respectively.
BCLKX is the bit clock and in this configuration is used for clocking both
received and transmitted serial data. MCLKR, MCLKX and BCLKX must
be synchronous and in this case they are the same signal, namely the
SCLK0 output generated by the ADSP-21xx processor. The BCLKR/
CLKSEL input, tied low, selects the frequency of MCLKX to be 2.048 MHz.
The ADSP-21xx must be programmed for internal SCLK0 generation at
2.048 MHz.

CODEC

(National 

Seminconductor 

TP3054)

BCLKR/CLKSEL

MCLKR

BCLKX

MCLKX

FSR

DR

FSX

DX

VFRO

VFXI+

TFS0

DT0

RFS0

DR0

SCLK0

ADSP-21xx

(Serial Port 0)

From Input 
Amplifier

To Output 
Amplifier

Digital 
Ground

Figure 13.2  ADSP-21xx Serial Port (SPORT0) To CODEC

Summary of Contents for adsp-2100

Page 1: ...rface 1 10 1 4 ADSP 2100 FAMILY DEVELOPMENT TOOLS 1 10 1 5 ORGANIZATION OF THIS MANUAL 1 11 CHAPTER 2 COMPUTATIONAL UNITS 2 1 OVERVIEW 2 1 2 1 1 Binary String 2 1 2 1 2 Unsigned 2 1 2 1 3 Signed Numbers Twos Complement 2 1 2 1 4 Fractional Representation 1 15 2 2 2 1 5 ALU Arithmetic 2 2 2 1 6 MAC Arithmetic 2 3 2 1 7 Shifter Arithmetic 2 3 2 1 8 Summary 2 4 2 2 ARITHMETIC LOGIC UNIT ALU 2 5 2 2 1...

Page 2: ... 2 4 Denormalize 2 31 2 4 2 5 Normalize 2 33 CHAPTER 3 PROGRAM CONTROL 3 1 OVERVIEW 3 1 3 2 PROGRAM SEQUENCER 3 1 3 2 1 Next Address Select Logic 3 3 3 2 2 Program Counter PC Stack 3 4 3 2 3 Loop Counter Stack 3 4 3 2 4 Loop Comparator Stack 3 5 3 3 PROGRAM CONTROL INSTRUCTIONS 3 8 3 3 1 JUMP Instruction 3 8 3 3 1 1 Register Indirect JUMPs 3 8 3 3 2 CALL Instruction 3 9 3 3 3 DO UNTIL Loops 3 9 3 ...

Page 3: ...2 4 2 Circular Buffer Base Address Example 2 4 5 4 2 4 3 Circular Buffer Operation Example 1 4 5 4 2 4 4 Circular Buffer Operation Example 2 4 6 4 2 5 Bit Reverse Addressing 4 6 4 3 PROGRAMMNG DATA ACCESSES 4 7 4 3 1 Variables Arrays 4 7 4 3 2 Circular Buffers 4 8 4 4 PMD DMD BUS EXCHANGE 4 9 4 4 1 PMD DMD Block Diagram Discussion 4 9 CHAPTER 5 SERIAL PORTS 5 1 OVERVIEW 5 1 5 2 BASIC SPORT DESCRIP...

Page 4: ...SPORT TIMING CONSIDERATIONS 5 34 5 13 1 Companding Delay 5 34 5 13 2 Clock Synchronization Delay 5 34 5 13 2 1 Startup Timing 5 34 5 13 3 Internally Generated Frame Sync Timing 5 34 5 13 4 Transmit Interrupt Timing 5 36 5 13 5 Receive Interrupt Timing 5 36 5 13 6 Interrupt And Autobuffer Synchronization 5 38 5 13 7 Instruction Completion Latencies 5 38 5 13 8 Interrupt And Autobuffer Service Examp...

Page 5: ...Decimation Filter 8 4 8 2 2 2 High Pass Filter 8 5 8 3 D A CONVERSION 8 6 8 3 1 DAC 8 6 8 3 1 1 High Pass Filter 8 6 8 3 1 2 Interpolation Filter 8 7 8 3 1 3 Analog Smoothing Filter Programmable Gain Amp 8 8 8 3 2 Differential Output Amplifier 8 8 8 4 OPERATING THE ANALOG INTERFACE 8 9 8 4 1 Memory Mapped Control Registers 8 9 8 4 1 1 Analog Control Register 8 9 8 4 1 2 Analog Autobuffer Powerdown...

Page 6: ...TTL CMOS Clock 9 21 9 7 4 2 Systems Using A Crystal Internal Oscillator 9 22 9 7 5 Operation During Powerdown 9 23 9 7 5 1 Interrupts Flags 9 23 9 7 5 2 SPORTS 9 23 9 7 5 3 HIP During Powerdown 9 24 9 7 5 4 IDMA Port During Powerdown ADSP 2181 9 25 9 7 5 5 BDMA Port During Powerdown ADSP 2181 9 26 9 7 5 6 Analog Interface ADSP 21msp5x 9 26 9 7 6 Conditions For Lowest Power Consumption 9 26 9 7 7 P...

Page 7: ...emory 10 37 10 7 MEMORY INTERFACE SUMMARY ALL PROCESSORS 10 37 CHAPTER 11 DMA PORTS 11 1 OVERVIEW 11 1 11 2 BDMA PORT 11 2 11 2 1 BDMA Port Functional Description 11 4 11 2 2 BDMA Control Registers 11 4 11 2 3 Byte Memory Word Formats 11 9 11 2 4 BDMA Booting 11 9 11 2 4 1 Development Software Features for BDMA Booting 11 11 11 3 IDMA PORT 11 12 11 3 1 IDMA Port Pin Summary 11 12 11 3 2 IDMA Port ...

Page 8: ...terrupt Routine Discussion 12 11 CHAPTER 13 HARDWARE EXAMPLES 13 1 OVERVIEW 13 1 13 2 BOOT LOADING FROM HOST USING BUS REQUEST 13 2 13 3 SERIAL PORT TO CODEC INTERFACE 13 5 13 4 SERIAL PORT TO DAC INTERFACE 13 8 13 5 SERIAL PORT TO ADC INTERFACE 13 10 13 6 SERIAL PORT TO SERIAL PORT INTERFACE 13 12 13 7 80C51 INTERFACE TO HOST INTERFACE PORT 13 13 CHAPTER 14 SOFTWARE EXAMPLES 14 1 OVERVIEW 14 1 14...

Page 9: ... 11 15 6 MOVE READ WRITE 15 12 15 7 PROGRAM FLOW CONTROL 15 14 15 8 MISCELLANEOUS INSTRUCTIONS 15 16 15 9 EXTRA CYCLE CONDITIONS 15 18 15 9 1 Multiple Off Chip Memory Accesses 15 18 15 9 2 Wait States 15 18 15 9 3 SPORT Autobuffering DMA 15 18 15 10 INSTRUCTION SET SYNTAX 15 19 15 10 1 Punctuation Multifunction Instructions 15 19 15 10 2 Syntax Notation Example 15 19 15 10 3 Status Register Notati...

Page 10: ... 15 64 MOVE Register Move 15 65 Load Register Immediate 15 67 Data Memory Read Direct Address 15 69 Data Memory Read Indirect Address 15 70 Program Memory Read Indirect Address 15 71 Data Memory Write Direct Address 15 72 Data Memory Write Indirect Address 15 73 Program Memory Write Indirect Address 15 75 I O Space Read Write 15 76 PROGRAM FLOW JUMP 15 77 CALL 15 78 JUMP or CALL on Flag In Pin 15 ...

Page 11: ...PPENDIX A INSTRUCTION CODING A 1 OPCODES A 1 A 2 ABBREVIATION CODING A 7 APPENDIX B DIVISION EXCEPTIONS B 1 DIVISION FUNDAMENTALS B 1 B 1 1 Signed Division B 1 B 1 2 Unsigned Division B 2 B 1 3 Output Formats B 2 B 1 4 Integer Division B 3 B 2 ERROR CONDITIONS B 3 B 2 1 Negative Divisor Error B 3 B 2 2 Unsigned Division Error B 4 B 3 SOFTWARE SOLUTION B 4 APPENDIX C NUMERIC FORMATS C 1 OVERVIEW C ...

Page 12: ...Contents xiv APPENDIX D INTERRUPT VECTOR ADDRESSES D 1 INTERRUPT VECTOR ADDRESSES D 1 APPENDIX E CONTROL STATUS REGISTERS E 1 OVERVIEW E 1 INDEX ...

Page 13: ...system Complete reference material for programmers is also included 1 1 1 Functional Units Table 1 1 on the following page lists the main functional units of the ADSP 21xx architecture and shows which functions are included on each of the processors Computational Units Every processor in the ADSP 2100 family contains three independent full function computational units an arithmetic logic unit ALU ...

Page 14: ...ludes a multichannel option Timer A programmable timer counter with 8 bit prescaler provides periodic interrupt generation Host Interface Port The Host Interface Port HIP allows direct connection with no glue logic to a host processor The HIP is made up of 16 data pins and 11 control pins The HIP is extremely flexible and has provisions to allow simple interface to a variety of host processors For...

Page 15: ...ents In a single cycle any device in the family can Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computation In that same cycle processors which have the relevant functional units can also Receive and or transmit data via the serial port s Receive and or transmit data via the host interface port Receive...

Page 16: ... higher integration devices The ADSP 2171 ADSP 2181 and ADSP 21msp58 59 processors have a number of additional and enhanced instructions The ADSP 2100 family instruction set provides flexible data moves Multifunction instructions combine one or more data moves with a computation Every instruction can be executed in a single processor cycle The assembly language uses an algebraic syntax for readabi...

Page 17: ...ware to handle address pointer wraparound simplifying the implementation of circular buffers both on and off chip and reducing overhead thereby improving performance Zero Overhead Looping and Branching DSP algorithms are repetitive and are most logically expressed as loops The program sequencer in the ADSP 2100 family supports looped code with zero overhead combining excellent performance with the...

Page 18: ...ectly and provide hardware support for multiprecision computation as well The ALU performs a standard set of arithmetic and logic operations in addition to division primitives The MAC performs single cycle multiply multiply add and multiply subtract operations The shifter performs logical and arithmetic shifts normalization denormalization and derive exponent operations The shifter implements nume...

Page 19: ...aneously for dual operand fetches A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers The circular buffer feature is also used by the serial ports for automatic data transfers Refer to the Serial Ports chapter for additional information DAG1 can supply addresses to data memory only DAG2 can supply addresses to either data memory or progr...

Page 20: ...om two sources an absolute value specified in the instruction code direct addressing or the output of a data address generator indirect addressing Only indirect addressing is supported for data fetches from program memory The program memory data PMD bus can also be used to transfer data to and from the computational units through direct paths or via the PMD DMD bus exchange unit The PMD DMD bus ex...

Page 21: ...an be configured for an 8 bit data bus or 16 bit data bus a multiplexed address data bus or separate address and data buses and separate read and write strobes or a read write strobe and a data strobe 1 3 4 DMA Ports ADSP 2181 The ADSP 2181 contains two DMA ports and Internal DMA Port and a Byte DMA Port The IDMA port provides an efficient means of communication between a host system and the DSP T...

Page 22: ...as well as supporting the high level syntax of the instruction set In addition to supporting a full range of system diagnostics the Assembler provides flexible macro processing include files and modular code development Linker The Linker links separately assembled modules It maps the linked code and data output to the target system hardware as specified by the System Builder output Simulator The S...

Page 23: ...es the data address generators DAGs and the PMD DMD bus exchange unit Chapters 5 6 7 and 8 describe the additional functional units included in different members of the ADSP 2100 family See Table 1 1 for a list of the functions included in each device Chapter 5 Serial Ports describes the serial ports SPORT0 and SPORT1 Chapter 6 Timer explains the programmable interval timer Chapter 7 Host Interfac...

Page 24: ...timing diagrams as needed Chapter 14 Software Examples provides illustrative code for some important DSP and numerical algorithms Chapter 15 Instruction Set Reference provides a detailed description of each ADSP 21xx instruction The Appendices provide reference material and further details on specific issues Appendix A Instruction Coding gives the complete set of opcodes and specifies the bit patt...

Page 25: ...signed magnitude ones complement BCD or excess n formats 2 1 1 Binary String This is the simplest binary notation sixteen bits are treated as a bit pattern Examples of computation using this format are the logical operations NOT AND OR XOR These ALU operations treat their operands as binary strings with no provision for sign bit or binary point placement 2 1 2 Unsigned Unsigned binary numbers may ...

Page 26: ...s and results as simple 16 bit binary strings except the signed division primitive DIVS Various status bits treat the results as signed the overflow AV condition code and the negative AN flag The logic of the overflow bit AV is based on twos complement arithmetic It is set if the MSB changes in a manner not predicted by the signs of the operands and the nature of the operation For example adding t...

Page 27: ...MAC automatically shifts the multiplier product P left one bit before transferring the result to the multiplier result register MR This shift causes the multiplier result to be in 1 31 format which can be rounded to 1 15 format Figure 2 7 in the MAC section of this chapter shows this In the integer mode the left shift does not occur For example if the operands are in the 16 0 format the 32 bit mul...

Page 28: ...rry Bit 16 bit unsigned same as operands ALU Saturation Signed same as operands MAC Fractional Multiplication P 1 15 Explicitly signed unsigned 32 bits 2 30 Multiplication MR 1 15 Explicitly signed unsigned 2 30 shifted to 1 31 Mult Add 1 15 Explicitly signed unsigned 2 30 shifted to 1 31 Mult Subtract 1 15 Explicitly signed unsigned 2 30 shifted to 1 31 MAC Saturation Signed same as operands MAC ...

Page 29: ... X input port of the ALU can accept data from two sources the AX register file or the result R bus The R bus connects the output registers of all the computational units permitting them to be used as input operands directly The AX register file is dedicated to the X input port and consists of two registers AX0 and AX1 These AX registers are readable and writable from the DMD bus The instruction se...

Page 30: ...he AR register can drive both the DMD bus and the R bus It is also loadable directly from the DMD bus The instruction set also provides for reading AR over the PMD bus but there is no direct connection this operation uses the DMD PMD bus exchange unit Figure 2 2 ALU Block Diagram X Y ALU R AZ AN AC AV AS AQ CI MUX MUX AR REGISTER MUX MUX 16 AF REGISTER AX REGISTERS 2 x 16 AY REGISTERS 2 x 16 16 16...

Page 31: ... such as during an interrupt service routine for extremely fast context switching A new task like an interrupt service routine can be executed without transferring current states to storage The selection of the primary or alternate bank of registers is controlled by bit 0 in the processor mode status register MSTAT If this bit is a 0 the primary bank is selected if it is a 1 the secondary bank is ...

Page 32: ...portions of multiprecision numbers 2 2 5 ALU Saturation Mode The AR register has a twos complement saturation mode of operation which automatically sets it to the maximum negative or positive value if an ALU result overflows or underflows This feature is enabled by setting bit 3 of the mode status register MSTAT When enabled the value loaded into AR during an ALU operation depends on the state of ...

Page 33: ...ith a 32 bit dividend numerator and a 16 bit divisor denominator yielding a 16 bit quotient executes in 16 cycles Higher and lower precision quotients can also be calculated The divisor can be stored in AX0 AX1 or any of the R registers The upper half of a signed dividend can start in either AY1 or AF The upper half of an unsigned dividend must be in AF The lower half of any dividend must be in AY...

Page 34: ...tedly to compute the remaining quotient bits For unsigned single precision divides the DIVQ instruction is executed 16 times to produce 16 quotient bits For signed single precision divides the DIVQ instruction is executed 15 times after the sign bit is computed by the DIVS operation DIVQ instruction shifts the AY0 register left by one bit so that the new quotient bit can be moved into the LSB posi...

Page 35: ... X IF AQ 0 15 LSBs Figure 2 4 DIVQ Operation The format of the quotient for any numeric representation can be determined by the format of the dividend and divisor Let NL represent the number of bits to the left of the binary point and NR represent the number of bits to the right of the binary point of the dividend DL represent the number of bits to the left of the binary point and DR represent the...

Page 36: ... produce an integer quotient in 16 0 format you must shift the dividend one bit to the left into 31 1 format before dividing Additional discussion and code examples can be found in the handbook Digital Signal Processing Applications Using the ADSP 2100 Family Volume 1 Dividend BBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB NL bits NR bits Divisor BB BBBBBBBBBBBBBB DL bits DR bits Quotient BBBB BBBBBBBBBBBB NL ...

Page 37: ...on saturation and clear to zero functions A feedback function allows part of the accumulator output to be directly used as one of the multiplicands on the next cycle 2 3 1 MAC Block Diagram Discussion Figure 2 6 on the following page shows a block diagram of the multiplier accumulator The multiplier has two 16 bit input ports X and Y and a 32 bit product output port P The 32 bit product is passed ...

Page 38: ...GISTER MY REGISTERS 2 x 16 24 16 16 X Y MULTIPLIER P MUX MX REGISTERS 2 x 16 16 16 32 16 MR1 REGISTER MR2 REGISTER MR0 REGISTER 16 8 M U X R0 R1 R2 MUX MUX MUX 40 MV 16 PMD BUS DMD BUS 16 UPPER R BUS ADD SUBTRACT Figure 2 6 MAC Block Diagram ...

Page 39: ...de input to the multiplier while either one simultaneously drives the DMD bus The output of the adder subtracter goes to either the MF register or the MR register The MF register is a feedback register which allows bits 16 31 of the result to be used directly as the multiplier Y input on a subsequent cycle The 40 bit adder subtracter register MR is divided into three sections MR2 MR1 and MR0 Each ...

Page 40: ...MR register MR X Y Multiply X and Y operands and subtract result from MR register 0 Clear result MR to zero The ADSP 2100 family provides two modes for the standard multiply accumulate function fractional mode for fractional numbers 1 15 and integer mode for integers 16 0 In the fractional mode the 32 bit P output is format adjusted that is sign extended and shifted one bit to the left before bein...

Page 41: ... 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MR2 MR1 MR0 P SIGN MULTIPLIER P OUTPUT 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MR2 MR1 MR0 31 31 31 31 31 31 31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P SIGN MULTIPLIER P OUTPUT Figure 2 7 Fractional Multiplier Result Format Figure 2 8 Integer Multiplier Result Format ...

Page 42: ...are used when multiplying the upper portion of a signed multiprecision number with the lower portion of another or when multiplying a signed single precision number by an unsigned single precision number The unsigned x unsigned mode is used when multiplying unsigned single precision numbers or the non upper portions of two signed multiprecision numbers 2 3 2 3 MAC Input Output Registers The source...

Page 43: ...ne bits of MR are not all ones or all zeros The MR register has a saturation capability which sets MR to the maximum positive or negative value if an overflow or underflow has occurred The saturation operation depends on the overflow status bit MV in the processor arithmetic status ASTAT and the MSB of the MR2 register The following table summarizes the MR saturation operation MV MSB of MR2 MR con...

Page 44: ... add a 1 into bit position 15 of the adder chain This method causes a net positive bias since the midway value when MR0 0x8000 is always rounded upward The accumulator eliminates this bias by forcing bit 16 in the result output to zero when it detects this midway point This has the effect of rounding odd MR1 values upward and even MR1 values downward yielding a zero large sample bias assuming unif...

Page 45: ... with MR0 set to 0x8000 will round up rather than only rounding odd MR1 values up For example MR value before RND biased RND result unbiased RND result 00 0000 8000 00 0001 8000 00 0000 8000 00 0001 8000 00 0002 8000 00 0002 8000 00 0000 8001 00 0001 8001 00 0001 8001 00 0001 8001 00 0002 8001 00 0002 8001 00 0000 7FFF 00 0000 7FFF 00 0000 7FFF 00 0001 7FFF 00 0001 7FFF 00 0001 7FFF This mode only...

Page 46: ... a set of registers The shifter input SI register provides input to the shifter array and the exponent detector The SI register is 16 bits wide and is readable and writable from the DMD bus The shifter array and the exponent detector also take as inputs AR SR or MR via the R bus The shifter result SR register is 32 bits wide and is divided into two 16 bit sections SR0 and SR1 The SR0 and SR1 regis...

Page 47: ...cle and written at the end of the cycle All register reads therefore read values loaded at the end of a previous cycle A new value written to a register cannot be read out until a subsequent cycle This allows an input register to provide an operand to the shifter at the beginning of the cycle and be updated with the next operand at the end of the same cycle It also allows a result register to be s...

Page 48: ...ignal determines the reference point for the shifting In the HI state all shifts are referenced to SR1 the upper half of the output field and in the LO state all shifts are referenced to SR0 the lower half The HI LO reference feature is useful when shifting 32 bit values since it allows both halves of the number to be shifted with the same control code HI LO reference signal is selectable each tim...

Page 49: ...GHIJ KLMNPR00 00000000 7 9 XXXXXXXA BCDEFGHI JKLMNPR0 00000000 8 8 XXXXXXXX ABCDEFGH IJKLMNPR 00000000 9 7 XXXXXXXX XABCDEFG HIJKLMNP R0000000 10 6 XXXXXXXX XXABCDEF GHIJKLMN PR000000 11 5 XXXXXXXX XXXABCDE FGHIJKLM NPR00000 12 4 XXXXXXXX XXXXABCD EFGHIJKL MNPR0000 13 3 XXXXXXXX XXXXXABC DEFGHIJK LMNPR000 14 2 XXXXXXXX XXXXXXAB CDEFGHIJ KLMNPR00 15 1 XXXXXXXX XXXXXXXA BCDEFGHI JKLMNPR0 16 0 XXXXXX...

Page 50: ...fter sign SS bit which is loaded into the arithmetic status register ASTAT The sign bit is the same as the MSB of the shifter input except when AV is set when AV is set in HI extend state the MSB is inverted to restore the sign bit of the overflowed value In the LO state the input is interpreted as the lower half of a double precision number In the LO state the exponent detector interprets the SS ...

Page 51: ...D 9 0 SSSSSSSS SSNDDDDD 9 SSSSSSSS SSSNDDDD 10 0 SSSSSSSS SSSNDDDD 10 SSSSSSSS SSSSNDDD 11 0 SSSSSSSS SSSSNDDD 11 SSSSSSSS SSSSSNDD 12 0 SSSSSSSS SSSSSNDD 12 SSSSSSSS SSSSSSND 13 0 SSSSSSSS SSSSSSND 13 SSSSSSSS SSSSSSSN 14 0 SSSSSSSS SSSSSSSN 14 SSSSSSSS SSSSSSSS 15 0 SSSSSSSS SSSSSSSS 15 LO Mode SS Shifter Array Input Output S NDDDDDDD DDDDDDDD 15 S SNDDDDDD DDDDDDDD 16 S SSNDDDDD DDDDDDDD 17 S S...

Page 52: ... shift logical shift and normalize can be optionally specified with SR OR and HI LO modes to facilitate multiprecision operations SR OR logically ORs the shift result with the current contents of SR This option is used to join two 16 bit quantities into a 32 bit value in SR When SR OR is not used the shift value is passed through to SR directly The HI and LO modifiers reference the shift to the up...

Page 53: ...alizes it to a value certain to be less than any actual exponents detected B Process the first array element Array 1 11110101 10110001 Exponent 3 3 SB 16 SB gets 3 C Process next array element Array 2 00000001 01110110 Exponent 6 6 3 SB remains 3 D Continue processing array elements When and if an array element is found whose exponent is greater than SB that value is loaded into SB When all array ...

Page 54: ...truction The data value controlling the shift is an 8 bit signed number The SE register is not used or changed by an immediate shift The following example shows the input value downshifted relative to the upper half of SR SR1 This is the HI version of the shift SI 0xB6A3 SR LSHIFT SI BY 5 HI Input 10110110 10100011 Shift value 5 SR 00000101 10110101 00011 000 000000 Here is the same input value sh...

Page 55: ...t and shift code SI 0xB6A3 SR ASHIFT SI BY 5 HI Input 10110110 10100011 Shift value 5 SR 11111101 10110101 00011 000 00000000 2 4 2 4 Denormalize Denormalizing refers to shifting a number according to a predefined exponent The operation is effectively a floating point to fixed point conversion Denormalizing requires a sequence of operations First the SE register must contain the exponent value Thi...

Page 56: ...is processed Always select a logical shift for the lower half of the input Likewise the second half processed must use the SR OR option to avoid overwriting the previous half of the output value Modifier LO SR OR Shift operation Logical SE 3 Second Input 01110110 01011101 lower half of desired result SR 11110110 11010100 011 01110 11001011 Here is the same input processed in the reverse order The ...

Page 57: ...modifier The second stage uses the NORM instruction NORM recognizes HI and LO and also has the SR OR option NORM uses the negated value of the SE register as its shift control code The negated value is used so that the shift is made in the correct direction Here is a normalization example for a single precision input SE EXP AR HI Detects Exponent With Modifier HI Input 11110110 11010100 SE set to ...

Page 58: ...he correct exponent value the order of operations is immaterial The first half whether HI or LO is normalized without the SR OR and the second half is normalized with SR OR to create one double precision value in SR The HI and LO modifiers identify which half is being processed Here is a complete example of a typical double precision normalization 1 Detect Exponent Modifier HI First Input 11110110...

Page 59: ...be upper half SE set to 15 2 Detect Exponent Modifier LO Second Input 11110110 11010100 SE now set to 19 3 Normalize Modifier HI No SR OR SE 19 negated First Input 11111111 11111111 SR 00000000 00000000 00000000 00000000 All values of SE less than 15 resulting in a shift of 16 or more upshift the input completely off scale 4 Normalize Modifier LO SR OR SE 19 negated Second Input 11110110 11010100 ...

Page 60: ...ent Modifier HIX SE gets set to 1 2 Normalize Modifier HI SE 1 AR 11111010 00110010 SR 01111101 00011001 The AC bit is supplied as the sign bit shown in bold above The HIX operation executes properly whether or not there has actually been an overflow Consider this example AR 11100011 01011011 AV 0 indicating no overflow AC 0 not meaningful if AV 0 1 Detect Exponent Modifier HIX SE set to 2 2 Norma...

Page 61: ...tial instruction execution zero overhead looping sophisticated interrupt servicing and single cycle branching with jumps and calls both conditional and unconditional Figure 3 1 on the following page shows a block diagram of the program sequencer Each functional block of the sequencer is discussed is detail in this chapter This chapter discusses both program sequencer logic and the following instru...

Page 62: ...ESS MUX PC STACK PMA BUS MUX STATUS REGISTERS STATUS STACK COUNT STACK CNTR Counter CE OUT CONDITION CODE ADDRESS OF JUMP CALL FUNCTION FIELD ADDRESS OF LAST INSTRUCTION IN LOOP TERMINATION CONDITION from INSTRUCTION REGISTER LOOP COMPARATOR ARITHMETIC STATUS from ALU INTERRUPTS MUX MUX from FI Pin Figure 3 1 Program Sequencer Block Diagram ...

Page 63: ...he PC incrementer is driven onto the PMA bus and is loaded back into the program counter to begin the next cycle The PC stack is used as the source for the next address when a return from subroutine or return from interrupt is executed The top stack value is also used as the next address when returning to the top of a DO UNTIL loop The instruction register provides the next address when a direct j...

Page 64: ...e of the PC stack This instruction uses the pseudo register TOPPCSTACK described at the end of this chapter The output of the next address multiplexer is fed back to the PC which normally reloads it at the end of each processor cycle In the case of a register indirect jump however DAG2 drives the PMA bus with the next instruction address and the PC is loaded directly from the PMA bus 3 2 3 Loop Co...

Page 65: ...he counter because a stack location would be wasted on the invalid counter value There is no valid value in the counter after a system reset and also after the CE condition is tested when the count stack is empty The count stack empty status bit in the SSTAT register indicates when the stack is empty The second exception is provided explicitly by the special purpose syntax OWRCNTR overwrite counte...

Page 66: ...LU Overflow AV 1 NOT AV Not ALU Overflow AV 0 MV MAC Overflow MV 1 NOT MV Not MAC Overflow MV 0 NEG X Input Sign Negative AS 1 POS X Input Sign Positive AS 0 CE Counter Expired FOREVER Always Table 3 1 DO UNTIL Termination Condition Logic When a DO UNTIL instruction is executed the 14 bit address of the last instruction and a 4 bit termination condition both contained in the DO UNTIL instruction a...

Page 67: ...on condition contained on top of the stack Case 2 If the last instruction in the loop is a jump call or return the explicitly stated instruction takes precedence over the implicit sequencing of the loop If the condition in the instruction is false normal loop sequencing takes place as described for Case 1 If the condition in the instruction is true however program control transfers to the jump cal...

Page 68: ...check for one loop termination at a time falling out of an inner loop by incrementing the PC would go beyond the end address of the outer loop if they terminated on the same instruction 3 3 PROGRAM CONTROL INSTRUCTIONS The following sections describe the primary instructions used to control program flow 3 3 1 JUMP Instruction The 14 bit jump address is embedded in the JUMP instruction word When a ...

Page 69: ...ired must be used as the DO UNTIL termination condition A simple example of this type of loop is as follows L0 10 setup circular buffer length register I0 data_buffer load pointer with first address of circular buffer M0 1 setup modify register for pointer increment CNTR 10 load counter with circular buffer length DO loop UNTIL CE repeat loop until counter expired DM I0 M0 0 initialize clear circu...

Page 70: ...ly read On the final pass through the loop the termination condition is true The PC stack is popped and execution continues with the instruction immediately following the last instruction of the loop The loop stack and count stack are also popped on this cycle 3 3 4 IDLE Instruction The IDLE instruction causes the processor to wait indefinitely in a low power state until an interrupt occurs When a...

Page 71: ... the instruction located at the appropriate interrupt vector address Tables 3 2 3 7 show the interrupts and associated vector addresses for each processor of the ADSP 2100 family Note that SPORT1 can be configured as either a serial port or as a collection of control pins including two external interrupt inputs IRQ0 and IRQ1 See Chapter 5 Serial Ports for more information about the configuration o...

Page 72: ... of this chapter Interrupt Source Interrupt Vector Address RESET startup 0x0000 IRQ2 0x0004 highest priority SPORT0 Transmit 0x0008 SPORT0 Receive 0x000C SPORT1 Transmit or IRQ1 0x0010 SPORT1 Receive or IRQ0 0x0014 Timer 0x0018 lowest priority Table 3 2 ADSP 2101 2115 Interrupts Interrupt Vector Addresses Interrupt Source Interrupt Vector Address RESET startup 0x0000 IRQ2 0x0004 highest priority S...

Page 73: ...n maskable 0x002C IRQ2 0x0004 IRQL1 level sensitive 0x0008 IRQL0 level sensitive 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 IRQE edge sensitive 0x0018 Byte DMA Interrupt 0x001C SPORT1 Transmit or IRQ1 0x0020 SPORT1 Receive or IRQ0 0x0024 Timer 0x0028 lowest priority Table 3 6 ADSP 2181 Interrupts Interrupt Vector Addresses Interrupt Source Interrupt Vector Address RESET startup or powerup...

Page 74: ...nstruction located at the interrupt vector address Upon return from the interrupt service routine the PC and status stacks are popped and execution resumes with the next instruction of the main program 3 4 2 Configuring Interrupts The following registers are used to configure interrupts ICNTL Determines whether interrupts can be nested and configures the external interrupts IRQ2 IRQ1 IRQ0 as edge ...

Page 75: ...2171 and ADSP 21msp58 59 The memory mapped HMASK register configures masking out the generation of individual read or write interrupts for each HIP data register The IMASK register can be set to mask or enable the servicing of all HIP read interrupts or all HIP write interrupts Both IMASK and HMASK must be set for HDR interrupts See Chapter 7 Host Interface Port for details 3 4 2 1 Interrupt Contr...

Page 76: ...ced the interrupt can then be recognized in software and serviced later The contents of IMASK are automatically pushed onto the status stack when entering an interrupt service routine and popped back when returning from the routine The configuration of IMASK upon entering the interrupt service routine is determined by the interrupt nesting enable bit bit 4 of ICNTL it may be altered though as part...

Page 77: ...lmn ijkl00 2 ijklmn ijk000 3 ijklmn ij0000 4 ijklmn i00000 5 high ijklmn 000000 ijklmn represents any pattern of ones and zeroes Table 3 8 IMASK Entering Interrupt Service Routines ADSP 2101 example 3 4 2 3 Global Enable Disable for Interrupts Global interrupt enable and disable instructions are available on the ADSP 2171 ADSP 2181 and ADSP 21msp58 59 processors ENA INTS DIS INTS Interrupts are en...

Page 78: ...n in Appendix E Control Status Registers The IFC registers of the ADSP 2111 ADSP 2171 and ADSP 21msp58 processors do not include force clear bits for Host Interface Port interrupts HIP interrupts cannot be forced or cleared in software 3 4 3 Interrupt Latency For the timer IRQx SPORT HIP and analog interface interrupts the latency from when an interrupt occurs to when the first instruction of the ...

Page 79: ...rvice routine is one cycle This one cycle latency is similar to that shown in Figure 3 3 for the timer interrupt of the ADSP 2101 2105 2111 2115 with the n instruction executing being the instruction that writes to IMASK to unmask the interrupt 3 4 3 1 Timer Interrupt Latency on ADSP 2101 ADSP 2105 ADSP 2115 ADSP 2111 For the timer interrupt on these processors the latency from when the interrupt ...

Page 80: ... the status stack when the processor responds to an interrupt they are popped upon return from the interrupt service routine with the RTI instruction The depth of the stack varies from processor to processor In each case sufficient stack depth is provided to accommodate nesting of all interrupts 3 5 1 Arithmetic Status Register ASTAT ASTAT is eight bits wide and holds the status information genera...

Page 81: ...d cannot be used until the next cycle Loading any ALU MAC or Shifter input or output registers directly from the DMD bus does not affect any of the arithmetic status bits Executing the ALU instruction PASS sets the AZ and AN bits for a given X or Y operand and clears AC 3 5 2 Stack Status Register SSTAT The SSTAT register is eight bits wide and holds information about the four processor stacks The...

Page 82: ...e set and subsequent pop operations have no effect on them In this situation then it is possible to have both the stack empty and stack overflow bits set for a given stack Assume for example that the four location count stack is overflowed by five successive pushes Five successive pops will restore the stack empty condition but will not clear the overflow condition The processor must be reset to c...

Page 83: ...s generator 1 DAG1 This is useful for reordering the input or output data of an FFT algorithm The ADSP 2100 family processors include a secondary register set which can be used to provide a fresh set of ALU MAC and Shifter registers at any time for example during execution of a subroutine The data register bank select bit of MSTAT determines which set of data registers is active 0 primary 1 second...

Page 84: ...rom internal program memory during a bus grant The processor will halt waiting for the buses to be released only when an access of external memory is required When GO mode is disabled the processor always halts during bus grant 3 6 CONDITIONAL INSTRUCTIONS The condition logic circuit of the program sequencer determines whether a conditional instruction is executed for example a jump call or arithm...

Page 85: ..._IN Not FI pin Last sample of FI pin 0 Only available on JUMP and CALL instructions Table 3 9 IF Condition Logic 3 7 TOPPCSTACK A special version of the Register to Register Move instruction Type 17 is provided for reading and popping or writing and pushing the top value of the PC stack The normal POP PC instruction does not save the value popped from the stack so to save this value into a registe...

Page 86: ...stack into AX0 NOP TOPPCSTACK I7 push contents of I7 onto PC stack Only the following registers may be used in the special TOPPCSTACK instructions ALU MAC Shifter DAG Registers Registers AX0 I0 I4 AX1 I1 I5 MX0 I2 I6 MX1 I3 I7 AY0 M0 M4 AY1 M1 M5 MY0 M2 M6 MY1 M3 M7 AR L0 L4 MR0 L1 L5 MR1 L2 L6 MR L3 L7 SI SE SR0 SR1 The Type 17 Register Move instruction is described in Chapter 15 Instruction Set ...

Page 87: ...be the last or next to last instruction in a Do Until loop Neither instruction 1 nor instruction 2 may be the pop read TOPPCSTACK instruction in the following code DO loop UNTIL CE AX0 DM I5 M5 instruction 2 loop instruction 1 3 There must be an equal number of pushes and pops within any Do Until loop including any normal POP PC instructions as well as the special TOPPCSTACK pop read and push writ...

Page 88: ...restrictions must be observed instruction 2 may not be either the pop read or push write TOPPCSTACK instruction If instruction 3 is also the last instruction of a Do Until loop then instruction 1 may not be the push write TOPPCSTACK instruction Program Control 3 3 28 ...

Page 89: ...generates only data memory addresses but provides an optional bit reversal capability DAG2 can generate both data memory and program memory addresses but has no bit reversal capability While the following discussion explains the internal workings of the DAGs bear in mind that the ADSP 2100 Family Development Software assembler and linker provides a direct method for declaring data buffers as circu...

Page 90: ...ting the appropriate mode bit in the mode status register MSTAT as discussed below or by using the ENA BIT_REV instruction Bit reversal facilitates FFT addressing The data address generators employ a post modify scheme after an indirect data access the specified M register M0 M3 in DAG1 M4 M7 in DAG2 is added to the specified I register to generate the updated I value The choice of the I and M reg...

Page 91: ... register contents are signed when reading an M register the upper 2 bits of the DMD bus are sign extended 4 2 2 Indirect Addressing The ADSP 2100 family processors allow two addressing modes for data memory fetches direct and register indirect Indirect addressing is accomplished by loading an address into an I index register and specifying one of the available M modify registers The L registers a...

Page 92: ...automatic modulo addressing for accessing circular data buffers To calculate the next address the modulus logic uses the following information The current location found in the I register unsigned The modify value found in the M register signed The buffer length found in the L register unsigned The buffer base address From these inputs the next address is calculated according to the formula Next A...

Page 93: ...uality rule specifies that the buffer length must be greater than the value 2n 1 n therefore must be three or less The only value of n that satisfies both inequalities is three Valid base addresses are multiples of 2n so in this example valid base addresses are multiples of eight 0x0008 0x0010 0x0018 and so on 4 2 4 2 Circular Buffer Base Address Example 2 As a second example assume a buffer lengt...

Page 94: ...in the following chart Individual address lines ADDRN Normal Order 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit reversed 00 01 02 03 04 05 06 07 08 09 10 11 12 13 Bit reversed addressing is a mode enabled and disabled by setting a mode bit in the mode status register MSTAT When enabled all addresses generated using index registers I0 3 are bit reversed upon output The modified valued stored back ...

Page 95: ...ectly and by name can be initialized from immediate values in a directive or from external data files and can be linear or circular with automatic wraparound An array is declared with a directive such as VAR DM coefficients 128 This declares an array of 128 16 bit values located in data memory DM The special operators and reference the address and length respectively of the array It could be refer...

Page 96: ... A common requirement in DSP is the circular buffer This is directly implemented by the processors data address generators DAGs using the L length registers First you must declare the buffer as circular VAR DM CIRC coefficients 128 This identifies it to the linker for placement on the proper address boundary Next you must initialize the L register typically using the assemblers s operator or a con...

Page 97: ...tly loaded or read when the full 24 bits are required Note that when reading data from program memory and data memory simultaneously there is a dedicated path from the upper 16 bits of the PMD bus to the Y registers of the computational units This read only path does not use the bus exchange circuit it is the path shown on the individual computational unit block diagrams 4 4 1 PMD DMD Block Diagra...

Page 98: ...be loaded from either the lower 8 bits of the DMD bus or the lower 8 bits of the PMD bus Its contents can also be read to the lower 8 bits of either bus PX register access follows the principles described below From the PMD bus the PX register is 1 Loaded automatically whenever data not an instruction is read from program memory to any register For example AX0 PM I4 M4 In this example the upper 16...

Page 99: ...ove instruction explicitly specifying the PX register as a source The upper 8 bits of the value read from the register are all zeroes AX0 PX Whenever any register is written out to program memory the source register supplies the upper 16 bits The contents of the PX register are automatically added as the lower 8 bits If these lower 8 bits of data to be transferred to program memory through the PMD...

Page 100: ...2 ADSP 2105 1 ADSP 2115 2 ADSP 2111 2 ADSP 2171 2 ADSP 2181 2 ADSP 21msp58 59 2 The serial ports designated SPORT0 and SPORT1 have some differences that are described in this chapter On the ADSP 2105 only SPORT1 is provided 5 2 BASIC SPORT DESCRIPTION Each SPORT has a five pin interface Pin Name Function SCLK Serial clock RFS Receive frame synchronization TFS Transmit frame synchronization DR Seri...

Page 101: ...tionally compressed in hardware then automatically transferred to the transmit shift register The bits in the shift register are shifted out on the SPORT s DT pin MSB first synchronous to the serial clock The receive portion of the SPORT accepts data from the DR pin synchronous to the serial clock When an entire word is received the data is optionally expanded then automatically transferred to the...

Page 102: ...anding in hardware each SPORT can perform A law and µ law companding according to CCITT recommendation G 711 See Section 5 10 Autobuffering with single cycle overhead using the DAGs each SPORT can automatically receive and or transmit an entire circular buffer of data with an overhead of only one cycle per data word Transfers between the SPORT and the circular buffer are automatic in this mode and...

Page 103: ...the TFS signal initiates the transmission of serial data Once transmission has begun each value written to the TX register is transferred to the internal transmit shift register and subsequently the bits are sent MSB first Each bit is shifted out on the rising edge of SCLK After the first bit MSB of a word has been transferred the SPORT generates the transmit interrupt The TX register is now avail...

Page 104: ...16 0x3FF9 SPORT0 multichannel receive word enables 15 0 0x3FF8 SPORT0 multichannel transmit word enables 31 16 0x3FF7 SPORT0 multichannel transmit word enables 15 0 0x3FF6 SPORT0 control register Multichannel mode controls Serial clock source Frame synchronization controls Companding mode Serial word length 0x3FF5 SPORT0 serial clock divide modulus determines frequency 0x3FF4 SPORT0 receive frame ...

Page 105: ...mber as the I register must be initialized to zero so that the circular buffer capability is not active For example I0 0x3FF2 M0 1 L0 0 DM I0 M0 0x6B27 the constant 0x6B27 is written to address pointed to by I0 pointer then modified by M0 DM I0 M0 0 address 0x3FF3 is set to 0 Either method works The second method requires only one cycle to configure the registers once the I M and L registers are i...

Page 106: ...ed to AY0 Because the SPORTs are interrupt driven these instructions would typically be executed within a interrupt service routine in response to a SPORT interrupt 5 4 SPORT ENABLE SPORTs are enabled through bits in the system control register This register is mapped to data memory address 0x3FFF Bit 12 enables SPORT0 if it is a 1 and bit 11 enables SPORT1 if it is a 1 Both of these bits 15 14 13...

Page 107: ...on 5 5 SERIAL CLOCKS Each SPORT operates on its own serial clock signal The serial clock SCLK can be internally generated or received from an external source The ISCLK bit bit 14 in either the SPORT0 or SPORT1 control register determines the SCLK source for the SPORT If this bit is a 1 the processor generates the SCLK signal if it is a 0 the processor expects to receive an external clock signal on...

Page 108: ...48 MHz 0 6 144 MHz Assumes CLKOUT frequency of 12 288 MHz Table 5 5 Common Serial Clock Frequencies Internally Generated If the value of SCLKDIV is changed while the internal serial clock is enabled the change in SCLK frequency takes effect at the start of the next rising edge of SCLK Note that the serial clock of SPORT1 the SCLK pin still functions when the port is being used in its alternate con...

Page 109: ...eginning of each serial word transfer The SPORTs have many ways of handling framing signals Transmit and receive framing are independent of each other All frame sync signals are sampled on the falling edge of the serial clock SCLK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFSR Receive Frame Sync Required TFSR Transmit Frame Sync Required SPORT0 Control Register 0x3FF6 SPORT1 Control Register 0x3FF2 TF...

Page 110: ...tions on both serial ports is unframed See Configuration Examples later in this chapter for examples of frame sync timing 5 7 2 Frame Sync Signal Source The processor can generate frame synchronization signals internally or receive them from an external source The sources for transmit frame syncs and receive frames syncs can be set independently If the internal receive frame sync IRFS bit or inter...

Page 111: ...he transmit TX0 or TX1 register at the time needed to ensure continuous data transmission after the last bit of the current word is transmitted the exact time depends on the framing mode being used see Normal and Alternate Framing Modes the next section The occurrence of the transmit frame sync is a result of the availability of data in the transmit register With an internally generated receive fr...

Page 112: ...a transmission or reception is continuous i e the last bit of one word is followed without a break by the first bit of the next word then the framing signal should occur in the same SCLK cycle as the last bit of each word In the alternate framing mode the framing signal should be asserted in the same SCLK cycle as the first bit of a word Received data bits are latched on the falling edge of SCLK a...

Page 113: ...ration Examples later in this chapter 5 7 4 Active High Or Active Low Framing sync signals for receiving and transmitting data can be either active high or active low and are configured independently If the invert RFS INVRFS bit or invert TFS INVTFS bit in the SPORT control register is a 0 the corresponding frame sync signal is active high If the INVRFS or INVTFS bit is a 1 the frame sync signal i...

Page 114: ...ronization and µ law companded 8 bit data This is a typical setup for communication with a combo codec SPORT1 is configured for an externally generated serial clock externally generated frame synchronization non companded 16 bit data and autobuffering This setup could be used to transfer data between processors in a multiprocessor system Only the needed memory mapped registers are initialized Noti...

Page 115: ...nd DM 0x3FFF AX0 PWAIT left as default IMASK 0x1E SPORT interrupts are enabled END SPORT INITIALIZATIONS Figure 5 9 Example SPORT Configuration Code 5 9 TIMING EXAMPLES This section contains examples of some combinations of the various framing options The timing diagrams show relationships between signals but are not scaled to show the actual timing parameters of the processor Consult the data she...

Page 116: ...oth Internal Framing Option and External Framing Option Shown Figure 5 10 SPORT Receive Normal Framing SCLK OUTPUT RFS DR RFS INPUT B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 SPORT Control Register Internal Frame Sync 0X10 XXX1 X0XX 0011 External Frame Sync 0X10 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 11 SPORT Continuous Receive Normal Framing ...

Page 117: ...1 X0XX 0011 External Frame Sync 0X11 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 12 SPORT Receive Alternate Framing SPORT Control Register Internal Frame Sync 0X11 XXX1 X0XX 0011 External Frame Sync 0X11 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 13 SPORT Continuous Receive Alternate Framing ...

Page 118: ...mal framing mode is shown for noncontinuous data any number of SCLK cycles between words and continuous data no SCLK cycles between words Figures 5 12 and 5 13 show noncontinuous and SPORT Control Register Internal Frame Sync 0X00 XXX1 X0XX 0011 External Frame Sync 0X00 XXX0 X0XX 0011 Figure 5 14 SPORT Receive Unframed Mode Normal Framing SPORT Control Register Internal Frame Sync 0X01 XXX1 X0XX 0...

Page 119: ...wn Note that the output meets the input timing requirement thus on processors with two SPORTs one SPORT could provide RFS for the other SPORT Control Register Internal Frame Sync 0XXX 101X 0XXX 0011 External Frame Sync 0XXX 100X 0XXX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5 16 SPORT Transmit Normal Framing SPORT Control Register Internal Frame Sync 0XXX 101X 0XX...

Page 120: ...wn Note There is an asynchronous delay between TFS input and DT See the appropriate data sheet for specifications Figure 5 18 SPORT Transmit Alternate Framing SPORT Control Register Internal Frame Sync 0XXX 111X 0XXX 0011 External Frame Sync 0XXX 110X 0XXX 0011 Both Internal Framing Option and External Framing Option Shown Note There is an asynchronous delay between TFS input and DT See the approp...

Page 121: ...t normal or at the same time as the first bit alternate This mode is appropriate for multiword bursts continuous reception SPORT Control Register Internal Frame Sync 0XXX 001X 0XXX 0011 External Frame Sync 0XXX 000X 0XXX 0011 Figure 5 20 SPORT Transmit Unframed Mode Normal Framing SPORT Control Register Internal Frame Sync 0XXX 011X 0XXX 0011 External Frame Sync 0XXX 010X 0XXX 0011 Note There is a...

Page 122: ... only at the start of the first word either one SCLK before the first bit normal or at the same time as the first bit alternate 5 10 COMPANDING AND DATA FORMAT Companding a contraction of COMpressing and exPANDing is the process of logarithmically encoding and decoding data to minimize the number of bits that must be sent Both SPORTs share the companding hardware one expansion and one compression ...

Page 123: ...the 16 bit value to be compressed to eight LSBs sign extended to the width of the transmit word before being written to the internal transmit register If the magnitude of the 16 bit value is greater than the 13 bit A law or 14 bit µ law maximum the value is automatically compressed to the maximum positive or negative value 5 10 1 Companding Operation Example With hardware companding interfacing to...

Page 124: ...le SPORT0 has priority while SPORT1 is forced to wait one cycle The effects of contention however are usually small The instruction set does not support loading both TX0 and TX1 in the same cycle consequently these operations will be naturally out of phase for contention in many cases The overhead cycle for the receive operation occurs prior to the receive interrupt and does not increase the time ...

Page 125: ... except on the ADSP 21msp58 59 which autobuffers only on SPORT0 Autobuffering uses the circular buffer addressing capability of the DAGs With autobuffering enabled each serial data word is transferred or if multichannel operation is enabled each active word is transferred to or from data memory in a single overhead cycle Autobuffering to program memory is not supported This overhead cycle occurs i...

Page 126: ...tion requiring multiple cycles the automatic transfer of individual data words has the highest priority of any operation short of RESET including all interrupts Thus it is possible for an autobuffer transfer to increase the latency of an interrupt response if the interrupt happens to coincide with the transfer Up to four autobuffered transfers can occur in the case that two or more are needed in t...

Page 127: ...as for other DAG operations the I and M registers must be in the same DAG numbered either 0 3 for DAG1 or 4 7 for DAG2 Consequently three bits identify the I register but only two bits are necessary to indicate the M register because the third bit MSB of the M register number must be the same as for the I register Likewise RIREG and RMREG indicate the numbers of the I and M registers respectively ...

Page 128: ...0 set to length of tx_buffer I1 rx_buffer I1 points to rx_buffer L1 rx_buffer L1 set to length of rx_buffer set up SPORT1 for autobuffering AX0 0x0013 TX uses I0 M0 RX uses I1 M0 DM 0x3FEF AX0 autobuffering enabled set up SPORT1 for 8 kHz sampling and 2 048 MHz SCLK AX0 255 set RFSDIV to 255 for 8 kHz DM 0x3FF0 AX0 AX0 2 set SCLKDIV to 2 for 2 048 MHz SCLK DM 0x3FF5 AX0 set up SPORT1 for normal re...

Page 129: ...lexed Each subsequent word belongs to the next consecutive channel so that for example a 24 word block of data contains one word for each of 24 channels SPORT0 supports 32 or 24 channels and can automatically select words for particular channels while ignoring the others 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPORT0 Control Register Multichannel Version 0x3FF6 MCE Multichannel Enable 1 Multichannel...

Page 130: ...t 15 in SPORT0 s control register 0x3FF6 When this bit is a 1 multichannel mode is enabled and some control bits in the SPORT0 control register are redefined Bits affected by multichannel mode are shown in Figure 5 25 At reset bit 15 is cleared disabling multichannel mode and enabling normal operation Figure 5 25 SPORT0 Control Register With Multichannel Mode Enabled The state of the multichannel ...

Page 131: ... processor will select its word from the 24 or 32 word block For example setting bit 0 selects word 0 bit 12 selects word 12 and so on Figure 5 27 SPORT0 Multichannel Word Enable Registers 5 12 2 Multichannel Operation Received words for channels that are not enabled are ignored that is no interrupts are generated for these words no autobuffering occurs and no data is written to the RX0 register L...

Page 132: ...f INVTDV is a 1 TDV is active low otherwise it is active high TDV can be used to enable additional buffer logic if required Figure 5 28 shows the start of a multichannel transfer As in earlier examples word length is four bits SLEN 3 and frame sync signals are active high Multichannel frame delay MFD is one SCLK cycle For the purpose of illustration words 0 and 2 are selected for receiving and wor...

Page 133: ...sor cycle Second SPORT0 has priority over SPORT1 if both require an expansion or compression operation in the same cycle in this case SPORT1 must wait one processor cycle See the section on companding earlier in this chapter for more details on companding 5 13 2 Clock Synchronization Delay Some SPORT timings depend on the processor clock Other timings depend on the serial clock SCLK0 or SCLK1 Thes...

Page 134: ...rial port transmit interrupt The latency depends on five factors the frequency of the serial clock whether or not companding is enabled whether or not there is contention for the companding circuit whether the current word has finished transmitting and the logic level of the SCLK Serial Clock TX Written Processor Clock High Low High MSB Transmitted Alternate Framing Serial Clock Processor Clock Hi...

Page 135: ...There is additional delay if the previous data transmission has not Interrupt or Autobuffer Request TFS DT SCLK BIT3 BIT2 BIT1 BIT0 Figure 5 31 SPORT Interrupt or Autobuffer Timing Transmit 4 Bit Words No Companding completed the TX register cannot be loaded into the transmit shift register until the previous transmission is complete 5 13 4 Transmit Interrupt Timing Once the MSB has been transmitt...

Page 136: ...eiver portion of the SPORT latches data on the DR pin on the falling edges of SCLK Receive interrupt timing differs from transmit interrupt timing The receive interrupt or autobuffer request occurs only after an entire word is FIgure 5 33 SPORT Interrupt or Autobuffer Timing Receive 4 Bit Words Companding Enabled Interrupt or Autobuffer Request RFS DR SCLK BIT3 BIT2 BIT1 BIT0 Interrupt or Autobuff...

Page 137: ...e companding circuitry Companding latencies as discussed above occur prior to generation of a receive interrupt Servicing the receive interrupt is subject to the same latencies as other interrupts 5 13 6 Interrupt Autobuffer Synchronization The serial ports are treated as an asynchronous system to the processor even if the processor is providing the serial clock Internal to the processor is a circ...

Page 138: ...ernal memory wait states Bus request when an external access is required in go mode Bus request with go mode disabled Multiple external accesses required for a single instruction Request CLKOUT EXEC A B FETCH INT INT Sync Delay NOP Instruction Fetch Vector Execute First Instruction Of Interrupt Routine Figure 5 35 Interrupt Service Example A pending higher priority autobuffer or interrupt request ...

Page 139: ... the same for a receive or a transmit interrupt request An additional latency cycle is consumed due to the fetching of the first instruction of the interrupt routine The interrupt can only be serviced on an instruction cycle boundary The above example in Figure 5 35 assumes all instructions are completed in one processor cycle Figure 5 36 shows the result of an autobuffer request that meets the se...

Page 140: ...UTOBUFFER D AUTOBUFFER Expand RX1 RX0 Autobuffer Transfer RX1 Autobuffer Transfer Figure 5 38 Receive Companding Example With Both Serial Ports processor cycle 5 13 9 Receive Companding Latency In addition to the cycles used for synchronization there are some additional delays possible due to receive companding The synchronized request is used by the processor to decide when to write the receive C...

Page 141: ...ure 5 40 Using One Index Register for Transmit and Receive Autobuffer receive autobuffer requests with companding enabled 5 13 10Interrupts With Autobuffering Enabled When autobuffering is enabled SPORT interrupts occur when the address modification done during the autobuffer operation causes a modulus wraparound The synchronization delay applies to this type of interrupt as well An example is sho...

Page 142: ...cycles between the requests If the processor is subject to bus requests wait states or other latencies which are longer than 11 2 serial clock cycles both autobuffer operations may be held off Since the transmit autobuffer has a higher priority it s request will occur first Because of the priority of the autobuffer requests the use of a single I register more difficult or even impossible in some c...

Page 143: ...periods can range up to 1 34 seconds Timer interrupts can be masked cleared and forced in software if desired For additional information refer to the section Interrupts in Chapter 3 Program Control 6 2 TIMER ARCHITECTURE The timer includes two 16 bit registers TCOUNT and TPERIOD and one 8 bit register TSCALE The extended mode control instruction enables and disables the timer by setting and cleari...

Page 144: ...n the number of cycles between decrements of TCOUNT For example if the value in TSCALE register is 0 the counter register decrements once every cycle If the value in TSCALE is 1 the counter decrements once every 2 cycles Figure 6 2 shows the timer block diagram TSCALE TPERIOD CLKOUT Timer Enable Prescale Logic TCOUNT Decrement Zero Count Register Load Logic Timer Interrupt Timer Enable 16 16 8 DMD...

Page 145: ...ter begins Because TSCALE is 1 TCOUNT is decremented on every other cycle The reloading of TCOUNT and continuation of the counting occurs as shown during the interrupt service routine Cycle TCOUNT Action n 4 TPERIOD loaded with 5 n 3 TSCALE loaded with 1 n 2 TCOUNT loaded with 5 n 1 5 ENA TIMER executed n 5 since TSCALE 1 no decrement n 1 5 decrement TCOUNT n 2 4 no decrement n 3 4 decrement TCOUN...

Page 146: ...erval from subsequent interrupts load TCOUNT with a different value from TPERIOD The formula for the first interrupt is TCOUNT 1 TSCALE 1 If you write a new value to TSCALE or TCOUNT the change is effective immediately If you write a new value to TPERIOD the change does not take effect until after TCOUNT is reloaded ...

Page 147: ...rating speed of the HIP is similar to that of the processor data bus A read or write operation can occur within a single instruction cycle Because the HIP is normally connected with devices that are much slower the 68000 for example can take four cycles to perform a bus operation the data transfer rate is usually limited by the host computer The host interface port is completely asynchronous to th...

Page 148: ... 1 Input HIP 8 16 Bit Host 0 16 bit 1 8 bit BMODE 1 Input HIP Boot Mode Select 0 normal EPROM 1 HIP HMD0 1 Input HIP Bus Strobe Select 0 RD WR 1 RW DS HRD HRW 1 Input HIP Read Strobe Read Write Select HWR HDS 1 Input HIP Write Strobe Host Data Strobe HMD1 1 Input HIP Address Data Mode 0 separate 1 multiplexed HD15 0 HAD15 0 16 Bidirectional HIP Data Address Data HA2 ALE 1 Input HIP Host Address 2 ...

Page 149: ...he address data and strobe pins as shown in Table 7 2 HMD0 configures the bus strobes selecting either separate read and write strobes or a single read write select and a host data strobe HMD1 configures the bus protocol selecting either separate address 3 bit and data 16 bit buses or a multiplexed 16 bit address data bus with address latch enable The timings of each of the four bus protocols are ...

Page 150: ...udes an associated HMASK register for masking interrupts generated by the HIP The HCI provides the control for reading and writing the host registers The two status registers provide status information to both the host and the ADSP 21xx core The HIP data registers HDR5 0 are memory mapped into internal data memory at locations 0x3FE0 HDR0 to 0x3FE5 HDR5 These registers can be thought of as a block...

Page 151: ...rwrite Bit HMASK HA2 ALE Figure 7 1 HIP Block Diagram The HSR registers are shown in Figure 7 2 which can be found on the following page Status information in HSR6 and HSR7 shows which HDRs have been written The lower byte of HSR6 shows which HDRs have been written by the host computer The upper byte of the HSR6 shows which HDRs have been written by the ADSP 21xx When an HDR register is read the c...

Page 152: ...rved All reserved bits and the software reset bit read as zeros The overwrite bit is the only bit in the HSRs that can be both written and read At reset all HSR bits are zeros except for the overwrite bit which is a one 7 4 HIP OPERATION The ADSP 21xx core can place a data value into one of the HDRs for retrieval by the host computer Similarly the host computer can place a data value into one of t...

Page 153: ...fers cannot occur the HACK pin is deasserted and the data pins are tristated Because a host computer that requires handshaking must wait for an acknowledgement from the ADSP 21xx it is possible to cause such a host to hang If when the host has initiated a transfer but has not yet received an acknowledgement the ADSP 21xx is reset then the acknowledgement can not be generated thus causing the host ...

Page 154: ...ults The ADSP 21xx HIP however includes synchronization circuitry which guarantees that the HIP status is constant during a read by either the ADSP 21xx core or the host This synchronization is illustrated in Figures 7 3 and 7 4 The status registers are updated by the ADSP 21xx and thus are synchronous with the ADSP 21xx processor clock but host accesses are asynchronous with respect to the ADSP 2...

Page 155: ...sets a flag output which is connected to a host interrupt input to signal the host that new data is ready to be transferred Flag outputs are discussed in detail in Chapter 9 System Interface If the ADSP 21xx passes data to the host through only one HDR then that HDR can be read directly by the host when it receives the interrupt If more than one HDR is used to pass data then the host must read the...

Page 156: ... bits for masking the generation of read and write interrupts for individual HDRs In order for a read or write of an HDR to cause an interrupt the HIP read or write interrupt must be enabled in IMASK and the read or write to the particular HDR must be enabled in HMASK HMASK is mapped to memory location 0x3FE8 IMASK is described in Chapter 3 Program Control A host write interrupt is generated whene...

Page 157: ...uests remain until all HIP interrupts are cleared by either reading or writing the appropriate HIP data register If the ADSP 21xx is reading registers that the host might be writing it is not certain that an interrupt will be generated To ensure that all host writes generate interrupts you must make sure that the ADSP 21xx is not reading the HDRs that the host is writing While servicing the interr...

Page 158: ...bus protocol selecting either separate address 3 bit and data 16 bit buses or a multiplexed 16 bit address data bus with address latch enable The HSIZE pin can be changed on a cycle by cycle basis although not shown in the following diagrams it has the same timing as the HRD HRW signal Figure 7 6 shows the HIP timing when both HMD0 0 and HMD1 0 HD15 0 HSEL HWR HACK HA2 0 DATA ADDRESS HSEL HRD HACK...

Page 159: ...K and for a read cycle the data 4 For a write cycle the host asserts the data 5 The host deasserts HRD or HWR and HSEL 6 The host deasserts the address and for a write cycle the data 7 The ADSP 21xx deasserts HACK and for a read cycle the data Figure 7 7 shows the HIP timing when HMD0 1 and HMD1 0 HMD0 HD15 0 DATA HSEL HDS HACK HA2 0 ADDRESS HRW HSEL HDS HACK HA2 0 ADDRESS HRW HD15 0 DATA Host Wri...

Page 160: ...e host asserts HDS and HSEL 3 The ADSP 21xx returns HACK and for a read cycle the data 4 For a write cycle the host asserts the data 5 The host deasserts HDS and HSEL 6 The host deasserts HRW and the address and for a write cycle the data 7 The ADSP 21xx deasserts HACK and for a read cycle the data Figure 7 8 shows the HIP timing when HMD0 0 and HMD1 1 HMD0 selects separate read and write strobes ...

Page 161: ...WR and HSEL 9 For a write cycle the host deasserts the data 10 The ADSP 21xx deasserts HACK and for a read cycle the data Figure 7 9 shows the HIP timing when HMD0 1 and HMD1 1 HMD0 selects a multiplexed read write select with data strobe and HMD1 selects multiplexed address and data buses HD0 HD2 are used for the address The timing for the read cycle and the write cycle is as follows HSEL HDS HAC...

Page 162: ...boot in either of two ways from external memory usually EPROM through the boot memory interface or from a host processor through the HIP The BMODE pin selects which type of booting occurs When BMODE 0 booting occurs through the memory interface This process is described in Chapter 10 Memory Interface When the BMODE 1 booting occurs through the HIP To generate a file for HIP booting use the HIP Spl...

Page 163: ...ction has been loaded into the HIP The ADSP 21xx reads the length of the boot load first then bytes are loaded from the highest address downwards This results in shorter booting times for shorter loads The number of instructions booted must be a multiple of eight The boot length value is given as length number of 24 bit program memory words 8 1 That is a length of 0 causes the HIP to load eight 24...

Page 164: ...at 997 HDR0 Lower Byte of Instruction at 997 HDR2 Middle Byte of Instruction at 997 HDR1 Upper Byte of Instruction at 0 HDR0 Lower Byte of Instruction at 0 HDR2 Middle Byte of Instruction at 0 HDR1 A 16 bit host boots the ADSP 21xx at the same rate as an 8 bit host Either type of host must write the same data to the same the HDRs in the same sequence HDR0 HDR2 HDR1 If a 16 bit host writes 16 bit d...

Page 165: ... on chip anti aliasing and anti imaging filters 16 bit sigma delta converters and programmable gain amplifiers ensures a highly integrated solution to voiceband analog processing requirements Sigma delta conversion technology eliminates the need for complex off chip anti aliasing filters and sample and hold circuitry The ADSP 21msp58 and ADSP 21msp59 contain the same analog interface they differ o...

Page 166: ...LTA DAC FILTER DAC PGA 16 VOLTAGE REFERENCE VREF REF FILTER BUF VIN NORM MUX VIN AUX DECOUPLE ADC PGA DIGITAL SIGMA DELTA MODULATOR Figure 8 1 Analog Interface Block Diagram ADSP 21msp58 59 8 2 A D CONVERSION The A D conversion circuitry of the ADSP 21msp58 59 s analog interface consists of an input multiplexer a programmable gain amplifier PGA and a sigma delta analog to digital converter ADC 8 2...

Page 167: ... control register Input signal level to the sigma delta modulator should not exceed the VINMAX specification listed in the ADSP 21msp58 59 Data Sheet Refer to Analog Input in the Design Considerations section of this chapter for more information An offset may be added to the input of the ADC in order to move the ADC s idle tones out of the 4 0 kHz speech band range This is selected by bit 10 of th...

Page 168: ...c IIR Sample frequency 40 0 kHz Passband cutoff 3 70 kHz Passband ripple 0 2 dB Stopband cutoff 4 0 kHz Stopband ripple 65 00 dB The passband cutoff frequency is defined to be the last point in the passband that meets the passband ripple specification Note that these specifications apply only to this filter and not to the entire ADC The specifications can be used to perform further analysis of the...

Page 169: ... IIR Sample frequency 8 0 kHz Passband cutoff 150 0 Hz Passband ripple 0 2 dB Stopband cutoff 100 0 Hz Stopband ripple 25 00 dB Note that these specifications apply only to this filter and not to the entire ADC The specifications can be used to perform further analysis of the exact characteristics of the filter for example using a digital filter design software package Figure 8 3 shows the frequen...

Page 170: ...en by the anti imaging interpolation filter These filters have the same characteristics as the ADC s anti aliasing decimation filter and digital high pass filter The output of the interpolation filter is fed to the DAC s digital sigma delta modulator which converts the 16 bit data to 1 bit samples at a 1 0 MHz rate The modulator noise shapes the signal such that errors inherent to the process are ...

Page 171: ...nterpolates the data rate from 8 kHz to 40 kHz and removes images produced by the interpolation process The output of this stage is then interpolated to 1 0 MHz and fed to the second stage a sinc4 digital filter that attenuates images produced by the 40 kHz to 1 0 MHz interpolation process The IIR low pass filter is a 10th order elliptic filter with a passband edge at 3 70 kHz and a stopband atten...

Page 172: ...acitor filter The Sallen Key filter has a 3 dB point at approximately 25 kHz 8 3 2 Differential Output Amplifier The ADSP 21msp58 59 s analog output signal VOUTP VOUTN is produced by a differential amplifier The differential amplifier meets specifications for loads greater than 2 kΩ RL 2 kΩ and has a maximum differential output voltage swing of 3 156 V peak to peak 3 17 dBm0 The DAC will drive loa...

Page 173: ... 4 1 Memory Mapped Control Registers Two memory mapped control registers are used to configure the ADSP 21msp58 59 s analog interface the analog control register and analog autobuffer powerdown register 8 4 1 1 Analog Control Register The analog control register located at address 0x3FEE in data memory is shown in Figure 8 4 This register configures the ADC input multiplexer ADC input gain PGA ADC...

Page 174: ...eserved bits 10 15 must always be set to 0 0 0 0 0 0 0 0 0 0 IG0 ADC Input Gain ADC PGA OG2 OG1 OG0 DAC Output Gain DAC PGA Gain 0 dB 6 dB 20 dB 26 dB IG1 0 0 1 1 IG0 0 1 0 1 IG1 IG0 ADC Input Gain ADC PGA ADC Offset DM 0x3FEE Figure 8 4 Analog Control Register 8 4 1 2 Analog Autobuffer Powerdown Register The analog autobuffer powerdown register located at address 0x3FEF in data memory is shown in...

Page 175: ...ts bits 5 6 of the analog control register The ADSP 21msp58 59 s powerdown function is described in the Powerdown section of Chapter 9 System Interface 8 4 2 Memory Mapped Data Registers There are two memory mapped data registers dedicated to the analog interface The 16 bit ADC receive data register is located at address 0x3FED in data memory The 16 bit DAC transmit data register is located at add...

Page 176: ... when autobuffering is disabled On the receive side the ADC interrupt is generated each time an A D conversion cycle is completed and the 16 bit data word is available in the ADC receive register On the transmit side the DAC interrupt is generated each time a D A conversion cycle is completed and the DAC transmit register is ready for the next 16 bit data word Both interrupts are generated simulta...

Page 177: ... analog interface IMASK 0x8 enable analog receive interrupt wait_loop IDLE wait for interrupt JUMP wait_loop ENDMOD Listing 8 1 ADSP 21msp58 59 Analog Loopback Program 8 4 3 2 Autobuffering Enabled In some applications it is advantageous to perform block data transfers between the analog converters and processor memory Analog interface autobuffering allows you to automatically transfer blocks of d...

Page 178: ...call autobuffer switch irq1v RTI NOP NOP NOP irq0v RTI NOP NOP NOP timerv RTI NOP NOP NOP pwrdwnv RTI NOP NOP NOP Before autobuffering is enabled separate circular buffers must be set up in data memory for the ADC receive and DAC transmit data This is accomplished by selecting I index and M modify registers in the analog autobuffer powerdown register see Figure 8 5 Transmit data autobuffered to th...

Page 179: ... DM flag_bit AR pass AX0 check buffer status IF NE JUMP fill_buff2 fill_buff1 SI 0x1 fill buff2 next time AY0 0x0013 JUMP done fill_buff2 SI 0x0 fill buff1 next time AY0 0x0203 JUMP done done DM codec_auto_ctrl AY0 DM flag_bit SI RTI ENDMOD Listing 8 2 ADSP 21msp58 59 Analog Autobuffer Program Receive and transmit autobuffering may be independently enabled and the two interrupts can occur and be s...

Page 180: ...pled approach that transfers most of the anti aliasing filtering into the digital domain the off chip anti aliasing filter need only be of low order Refer to the ADSP 21msp58 59 Data Sheet for more detailed information The ADSP 21msp58 59 s on chip ADC PGA programmable gain amplifier can be used when there is not enough gain in the input circuit The ADC PGA is configured by bits 9 and 0 IG1 IG0 of...

Page 181: ...nput resistance of the analog input VINNORM VINAUX 200 kΩ and the desired cutoff frequency The cutoff frequency should be less than or equal to 30 Hz The following equations should be used to determine the values for R1 C1 and C2 R1 should be less than or equal to 2 2 kΩ C2 should be greater than or equal to 0 027 µF C3 should be equal to C2 C2 RIN input resistance of ADSP 21msp58 59 200 kΩ f1 cut...

Page 182: ... coupled directly to a load or dc coupled to an external amplifier Figure 8 7 shows a simple circuit providing a differential output with ac coupling The capacitor of this circuit COUT is optional if used its value can be chosen as follows COUT The VOUTP VOUTN outputs must be used as differential outputs do not use either as a single ended output Figure 8 8 shows an example circuit which can be us...

Page 183: ...ilter Capacitance Figure 8 9 shows the recommended reference filter capacitor connections The capacitor grounds should be connected to the same star ground point as that of Figure 8 6 VOUT P VOUTN ADSP 21msp5x SSM 2141 1 5 7 4 12 V 12 V VOUT 0 1 µF 0 1 µF GND A GND A GND A BUF VOLTAGE REFERENCE 0 1µF 10µF STAR GROUND ADSP 21msp5x REF_FILTER VREF ...

Page 184: ... and ADSP 2111 processors operate with an input clock frequency equal to the instruction cycle rate The ADSP 2171 ADSP 2181 and ADSP 21msp58 59 processors operate with an input clock frequency equal to half the instruction rate for example a 16 67 MHz input clock produces a 33 MHz instruction rate 30 ns cycle time Device timing is relative to the internal clock rate which is indicated by the CLKOU...

Page 185: ...tes The relationship between the phases of CLKIN CLKOUT and the processor states is shown in Figure 9 2 for the ADSP 2101 ADSP 2105 ADSP 2115 and ADSP 2111 processors Figure 9 3 shows the same information for the ADSP 2171 ADSP 2181 and ADSP 21msp58 59 processors The phases of the internal processor clock are dependent upon the period of the external clock The CLKOUT output can be disabled on the ...

Page 186: ...etup time on a given cycle it is recognized either in the current cycle or during the next cycle if it remains valid Edge sensitive interrupt requests are latched internally so that the request signal only has to meet the pulse width requirement To ensure the recognition of any asynchronous input however the input must be asserted for at least one full processor cycle plus setup and hold time Setu...

Page 187: ...erated by the processor during RESET except when disabled on the ADSP 2171 ADSP 2181 or ADSP 21msp58 59 The contents of the computation unit ALU MAC Shifter and data address generator DAG1 DAG2 registers are undefined following RESET When RESET is released the processor s booting operation takes place depending on the state of the processor s MMAP pin Program booting is described in Chapter 10 Mem...

Page 188: ...werup Context Reset Setting the PUCR bit in the SPORT1 Autobuffer Powerdown Control Register causes a reboot on recovery from powerdown Table 9 1 Software Forced Rebooting Tables 9 2 9 7 show the state of the processor registers after a software forced reboot The values of any registers not listed are unchanged by a reboot During booting and rebooting all interrupts including serial port interrupt...

Page 189: ...LE Timer scale register undefined unchanged Serial Port Control Registers memory mapped one set per SPORT ISCLK Internal serial clock 0 unchanged RFSR TFSR Frame sync required 0 unchanged RFSW TFSW Frame sync width 0 unchanged IRFS ITFS Internal frame sync 0 unchanged INVRFS INVTFS Invert frame sense 0 unchanged DTYPE Companding type format 0 unchanged SLEN Serial word length 0 unchanged SCLKDIV S...

Page 190: ...Timer count register undefined operates during reboot TPERIOD Timer period register undefined unchanged TSCALE Timer scale register undefined unchanged Serial Port 1 Control Registers memory mapped ISCLK Internal serial clock 0 unchanged RFSR TFSR Frame sync required 0 unchanged RFSW TFSW Frame sync width 0 unchanged IRFS ITFS Internal frame sync 0 unchanged INVRFS INVTFS Invert frame sense 0 unch...

Page 191: ...ernal serial clock 0 unchanged RFSR TFSR Frame sync required 0 unchanged RFSW TFSW Frame sync width 0 unchanged IRFS ITFS Internal frame sync 0 unchanged INVRFS INVTFS Invert frame sense 0 unchanged DTYPE Companding type format 0 unchanged SLEN Serial word length 0 unchanged SCLKDIV Serial clock divide undefined unchanged RFSDIV RFS divide undefined unchanged Multichannel word enable bits undefine...

Page 192: ...owerdown force 0 unchanged PUCR Powerup context reset 0 unchanged XTALDIS XTAL pindrive disable 0 unchanged during powerdown XTALDELAY Delay startup from powerdown 0 unchanged 4096 cycles Serial Port Control Registers memory mapped one set per SPORT ISCLK Internal serial clock 0 unchanged RFSR TFSR Frame sync required 0 unchanged RFSW TFSW Frame sync width 0 unchanged IRFS ITFS Internal frame sync...

Page 193: ...tus 0 unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged IFC Interrupt force clear 0 0 Control Registers memory mapped BWAIT Boot memory wait states 3 unchanged BPAGE Boot page 0 unchanged SPORT1 configure Configuration 1 unchanged SPE0 SPORT0 enable 0 unchanged SPE1 SPORT1 enable 0 unchanged DWAIT0 4 Data memory wait states 7 unchanged PWAIT Program memory wait 7 u...

Page 194: ...PMOVLAY Program memory overlay select 0 unchanged memory mapped DWAIT Data memory overlay wait states 0x7 unchanged PWAIT Program memory overlay wait states 0x7 unchanged BMWAIT Byte memory wait states 0x7 unchanged IOWAIT0 3 I O memory wait states 0x7 unchanged CMSSEL Composite memory select 0xB unchanged Programmable Flag Data Control Registers memory mapped PFDATA Programmable flag data undefin...

Page 195: ...rdown force 0 unchanged PUCR Powerup context reset 0 unchanged XTALDIS XTAL pindrive disable 0 unchanged during powerdown XTALDELAY Delay startup from powerdown 0 unchanged 4096 cycles Serial Port Control Registers memory mapped one set per SPORT ISCLK Internal serial clock 0 unchanged RFSR TFSR Frame sync required 0 unchanged RFSW TFSW Frame sync width 0 unchanged IRFS ITFS Internal frame sync 0 ...

Page 196: ... set for a BDMA boot the values in the BDMA registers change as shown in Table 9 8 Register Process Description Value Before Boot Value After Boot BIAD BDMA Internal Memory Address 0 0x20 Set for internal address 0 BEAD BDMA External Memory Address 0 0x60 Set for external address 0 BTYPE BDMA Transfer Word Type 0 0 Set for 24 bit program memory words BDIR BDMA Transfer Direction 0 0 Set to transfe...

Page 197: ...ge sensitive Level sensitive interrupts operate by asserting the interrupt request line IRQx until the request is recognized by the processor Once recognized the request must be deasserted before unmasking the interrupt so that the DSP does not continually respond to the interrupt In contrast edge triggered interrupt requests are latched when any high to low transition occurs on the interrupt line...

Page 198: ... and IRQ1 an interrupt request can be generated This interrupt request can be cleared with the use of the IFC register 9 6 FLAG PINS All ADSP 21xx processors provide flag pins The alternate configuration of SPORT1 includes a Flag In FI pin and a Flag Out FO pin The configuration of SPORT1 as either a serial port or as flags and interrupts is selected by bit 10 of the processor s system control reg...

Page 199: ... Register determines the flag direction 1 output and 0 input The Programmable Flag Data Register is used to read and write the values on the pins Data being read from a pin configured as an input is synchronized to the processor s clock Pins configured as outputs drive the appropriate output value When the PFDATA register is read any pins configured as outputs will read back the value being driven...

Page 200: ...sor data sheet for exact power consumption specifications The powerdown feature is useful for applications where power conservation is necessary for example in battery powered operation Features of powerdown include Internal clocks are disabled Processor registers and memory contents are maintained Ability to recover from powerdown in less than 100 CLKIN cycles Ability to disable internal oscillat...

Page 201: ...ter or Analog Autobuffer Powerdown Control Register on the ADSP 21msp58 59 This control register is memory mapped at location 0x3FEF and is shown in Figure 9 6 SPORT1 Autobuffer Powerdown Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XTALDIS XTAL Pin Drive Disable During Powerdown 1 disabled 0 enabled XTAL pin should be disabled when no external crystal is connected XTALDELAY Delay Startu...

Page 202: ...cally this section of code is used to configure the powerdown state disable on chip peripherals and clear pending interrupts 4 The processor now enters powerdown mode when it executes an IDLE instruction while PWD is asserted The processor may take either one or two cycles to power down depending upon internal clock states during the execution of the IDLE instruction All register and memory conten...

Page 203: ...an External TTL CMOS Clock and Systems Using a Crystal and The Internal Oscillator You can also program one of two options directing the processor how to resume operation The context for exiting powerdown is set by bit 12 PUCR powerup context reset of the Powerdown Control Register If the PUCR control bit is cleared to 0 the processor will continue to execute instructions following the IDLE instru...

Page 204: ... bit is ignored 9 7 4 Startup Time After Powerdown The time required to exit the powerdown state depends on whether an internal or external oscillator is used and the method used to exit powerdown 9 7 4 1 Systems Using An External TTL CMOS Clock When the processor is in powerdown the external clock signal is ignored if the XTALDIS bit XTAL pin disable of the Powerdown Control Register is set to 1 ...

Page 205: ... no additional delay after start up from powerdown and drives the external crystal during powerdown In this configuration the oscillator will continue to operate and the processor will start executing instructions in less than 100 cycles after the low to high signal transition at the PWD pin The XTAL pin will also be driven and the powerdown power consumption will be higher than the 1 mW specifica...

Page 206: ...n be achieved 9 7 5 1 Interrupts And Flags Interrupts are latched and can be serviced if the processor exits powerdown without a context reset PUCR 1 Any activity on the interrupt or flag input pins during powerdown will increase the power consumption There should also be no resistive load on the flag output pins as with any active output pin if lowest power is desired 9 7 5 2 SPORTS The circuitry...

Page 207: ...hile in powerdown If internal serial clock is used there is no SPORT activity during powerdown the serial clock stops Lowest power dissipation is achieved when active SPORT pins are not changing during powerdown and are held at CMOS levels 9 7 5 3 HIP During Powerdown The circuitry of the Host Interface Port HIP is not directly affected by powerdown on the ADSP 2171 and ADSP 21msp58 59 The HIP is ...

Page 208: ...desire the host to communicate with other devices on the bus while the DSP processor is in powerdown HMD0 should be held low to avoid extra power to be dissipated When the HIP is put in other modes where data inputs are not active this is not a problem Lowest power dissipation is achieved when the HIP pins are not changing during powerdown and are held at CMOS levels 9 7 5 4 IDMA Port During Power...

Page 209: ...werdown the ADSP 21msp58 59 s analog interface separately from the processor as described in the Analog Interface chapter of this manual The analog interface does not work during powerdown and causes additional power to be dissipated if it is not disabled The following code example shows a powerdown interrupt routine for the ADSP 21msp58 59 Sample Powerdown Code located at address 0x002C pwd_int a...

Page 210: ...cillator is active unless XTALDIS bit is set CLKOUT O Driven HIGH XTAL O Driven HIGH if XTALDIS set inversion of CLKIN otherwise PWDACK O Driven HIGH PMS O Driven HIGH high impedance if bus granted DMS O Driven HIGH high impedance if bus granted BMS O Driven HIGH high impedance if bus granted IOMS O ADSP 2181 Driven HIGH high impedance if bus granted CMS O ADSP 2181 Driven HIGH high impedance if b...

Page 211: ... I ADSP 2181 Active if IS asserted IS I ADSP 2181 Active IAL I ADSP 2181 Active if IS asserted IAD I O ADSP 2181 Active if an operation in progress IACK O ADSP 2181 Active HSIZE I ADSP 2171 ADSP 21msp5x Active HMD0 I ADSP 2171 ADSP 21msp5x Active HMD1 I ADSP 2171 ADSP 21msp5x Active HSEL I ADSP 2171 ADSP 21msp5x Active HRD I ADSP 2171 ADSP 21msp5x Active HWR I ADSP 2171 ADSP 21msp5x Active HADR 2 ...

Page 212: ...n IDLE instruction is executed causing the processor to go into powerdown The CLKOUT and PWDACK signals are driven high by the processor At this point the input clock pin is ignored If the processor is put into the powerdown mode via the powerdown force bit in the powerdown control register the result is the same as described above The input clock is started and the PWD pin is brought high After t...

Page 213: ...on Maskable Interrupt The powerdown interrupt is never masked It is possible to use this interrupt for other purposes if desired The processor will not go into powerdown until an IDLE instruction is executed If an RTI is executed before the IDLE instruction then the processor returns from the powerdown interrupt and the powerdown sequence is aborted It is possible to place a series of instructions...

Page 214: ... memory data bus PMD The internal PMA bus and DMA bus are multiplexed into a single address bus which is extended off chip Likewise the internal PMD bus and DMD bus are multiplexed into a single external data bus The sixteen MSBs of the external data bus are used as the DMD bus external bus lines D23 8 are used for DMD15 0 There are three separate memory spaces data memory program memory and boot ...

Page 215: ...MS RD WR ADDR13 0 DATA23 0 AAAA AAAA AAAA ADDR DATA OPTIONAL AAAA AAAA AAAA AAAA ADDR DATA CS OE BOOT MEMORY e g EPROM 2764 27128 27256 27512 PROGRAM MEMORY DATA MEMORY PERIPHERALS 14 24 D23 22 A13 0 D15 8 D23 0 D23 8 A13 0 A13 0 XTAL MMAP DR1 or FI AA AA SERIAL DEVICE OPTIONAL DT1 or FO SCLK1 SPORT 1 DR0 DT0 TFS0 SCLK0 RFS0 SPORT 0 OE WE CS RFS1 or IRQ0 TFS1 or IRQ1 AA AA SERIAL DEVICE OPTIONAL O...

Page 216: ...dress and memory can be selected Two control lines indicate the direction of the transfer Memory read RD is active low signaling a read and memory write WR is active low for a write operation Typically you would connect PMS to CE Chip Enable RD to OE Output Enable and WR to WE Write Enable of your memory 10 2 1 External Program Memory Read Write On chip memory accesses do not drive any external si...

Page 217: ...Data In Data Out Address PMS DMS RD or WR or External Program Data Memory Read Write PWAIT 0 DWAIT 0 no wait states added Figure 10 2A Memory Read And Write No Wait States External Program Data Memory Read Write PWAIT 1 DWAIT 1 one wait state added Figure 10 2B Memory Read And Write One Wait State ...

Page 218: ...ows the same information for the processors with 1K internal program memory ADSP 2105 ADSP 2115 When MMAP 0 internal RAM occupies 2K words beginning at address 0x0000 In this configuration the boot loading sequence is automatically initiated when RESET is released as described in Boot Memory Interface When MMAP 1 words of external program memory begin at address 0x0000 and internal RAM is located ...

Page 219: ...onsequently if the processor is operating entirely from on chip memory it can fetch two operands and the next instruction on every cycle It can also fetch any one of these three from external memory with no performance penalty 10 2 3 ROM Program Memory Maps The ADSP 2172 and ADSP 21msp59 processors contain mask programmable ROM on chip The program memory maps for these processors are shown in Figu...

Page 220: ...External ROMENABLE 0 8K Internal ROM ROMENABLE 1 Figure 10 6 ADSP 2172 Program Memory Map 0000 07FF 0800 3FFF INTERNAL RAM LOADED FROM EXTERNAL BOOT MEMORY EXTERNAL ROM ENABLE 0 MMAP 0 0000 3FFF EXTERNAL ROM ENABLE 0 MMAP 1 37FF 3800 INTERNAL RAM NOT LOADED 0000 07FF 0800 17FF 1800 3FFF INTERNAL RAM LOADED FROM EXTERNAL BOOT MEMORY INTERNAL MASK PROGRAMMED ROM EXTERNAL ROM ENABLE 1 MMAP 0 17F0 17F...

Page 221: ...nal RAM location location 0x0000 0x0000 MMAP 1 No booting execution Standalone mode starts at external memory execution starts at location 0x0000 internal ROM location 0x0800 Table 10 1 Booting Mode for ADSP 2172 ADSP 21msp59 The ADSP 216x processors are memory variant versions of the ADSP 2101 and ADSP 2103 that contain factory programmed on chip ROM program memory The ADSP 2161 ADSP 2163 and ADS...

Page 222: ... MMAP 1 0x37FF 0x3800 2K INTERNAL ROM 2K INTERNAL ROM 10K EXTERNAL 0x07FF 0x0800 0x0FF0 Reserved 0x0FFF 0x1000 0x0FF0 Reserved 0x0FFF 0x1000 Figure 10 8 ADSP 2161 62 Program Memory Maps Figure 10 9 ADSP 2163 64 Program Memory Maps 12K x 24 INTERNAL ROM 2K x 24 EXTERNAL 2FFF 3000 3FFF 0000 2K EXTERNAL 3FFF 0000 MMAP 0 MMAP 1 2FFF 3000 2K x 24 INTERNAL ROM 10K X 24 INTERNAL ROM RESERVED 3800 37FF 07...

Page 223: ... operation Typically you would connect DMS to CE Chip Enable RD to OE Output Enable and WR to WE Write Enable of your memory 10 3 1 External Data Memory Read Write Internal data memory accesses are transparent to the external memory interface Only off chip accesses drive the memory interface Off chip data memory accesses follow the same sequence as off chip program memory accesses namely 1 The pro...

Page 224: ...isters are mapped into the top 1K of data memory addresses 0x3C00 0x3FFF The rest of the top 1K is reserved External data memory is available for additional data storage Figures 10 11 10 12 and 10 13 show the data memory maps for each ADSP 21xx processor AAAAA AAAAA AAAAA Memory Mapped Control Registers Reserved 0x3A00 0x0400 0x0000 1K External DWAIT0 1K External DWAIT1 10K External DWAIT2 1K Exte...

Page 225: ...ls of one speed while another zone was used with faster or slower peripherals Similarly slower and faster memories can be used for different purposes as long as they are located in different zones of the data memory map As shown in Figures 10 12 and 10 13 the ADSP 2171 ADSP 21msp58 59 and ADSP 2165 66 processors each have three wait state zones for external data memory 3BFF 3C00 37FF 3800 Data Mem...

Page 226: ... a separate field for each zone of external memory Each 3 bit field specifies the number 0 7 of wait states for the corresponding zone of memory all zones default to 7 wait states after RESET Figure 10 14 shows this control register for the ADSP 2101 ADSP 2111 ADSP 2105 ADSP 2115 and ADSP 2161 62 63 64 processors Figure 10 15 shows the register for the ADSP 2171 72 and ADSP 21msp58 59 processors o...

Page 227: ...ions and other types of devices can be mapped into external data memory Communication takes the form of reading and writing the memory locations associated with the device Some A D and D A converters require this type of interface The PORT directives in the System Builder and Assembler modules of the ADSP 2100 Family Development Software support this mapping Communication with a memory mapped devi...

Page 228: ...escribed in Chapter 7 BR is recognized during the booting sequence The bus is granted after completion of loading the current byte The ADSP 216x contain on chip program memory ROM on these devices no booting occurs 10 4 1 Boot Pages Boot memory is organized into eight pages each of which can be 8K bytes long Every fourth byte of a page is an empty byte except the first one which contains the page ...

Page 229: ...pped System Control Register see Figure 10 17 specifies which boot page is to be loaded To boot from a specific boot page set BPAGE to the desired page number and in the same memory mapped register set the boot force bit BFORCE When the boot force bit is set the software forced booting sequence starts Except for the page selection and possibly the number of wait states there is no difference betwe...

Page 230: ...tes The default value at reset is 3 wait states on the ADSP 2101 ADSP 2105 ADSP 2111 and ADSP 2115 BWAIT defaults to 7 wait states on the ADSP 2171 and ADSP 21msp58 Timing of the boot memory access is identical to that of external program memory or external data memory accesses except that the active strobe is BMS rather than PMS or DMS To address eight pages of 8K bytes each 16 bits are needed Th...

Page 231: ...order is upper byte lower byte middle byte The word pointer is then decremented This addresses the second to last 24 bit word in the EPROM For example to boot from page 0 the shortest allowable page with eight 24 bit words corresponding to a page length of 0 the following addresses would be generated see Figure 10 20 1 The first address generated is 0x0003 which reads the page length 2 The next ad...

Page 232: ... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 Bit Page Length Page 1 1 1 0 0 8 Bit Page Length Page 1 1 1 1 0 8 Bit Page Length Page 1 1 1 0 1 8 Bit Page Length Page 1 1 0 0 0 8 Bit Page Length Page 1 1 0 1 0 8 Bit Page Length Page 1 1 0 0 1 8 Bit Page Length Page 1 0 1 0 0 etc 1st Word 2nd Word Figure 10 18 Boot Memory Address Figure 10 19 Boot Memory Addresses ...

Page 233: ...sed Address Word 1 MSB Word 1 LSB Not Used 0000 0002 0003 0001 0004 0005 0006 0007 Word 6 USB Word 6 MSB Word 6 LSB 001B 001C 001D 001E 001F 001A 0019 0018 EPROM Order Addressed bytes 1st 5th 7th 6th 2nd 4th 3rd Page 0 Pagelength 0 1st word loaded 2nd word loaded Figure 10 20 Example of Boot Loading Order with Page 0 Pagelength 0 ...

Page 234: ...ranting the bus and the serial ports and host interface port on the ADSP 2111 ADSP 2171 ADSP 21msp5x remain active during a bus grant whether or not the processor core halts If the ADSP 21xx is performing an external access when the BR signal is asserted it will not grant the buses until the cycle after the access completes The sequence of events is illustrated in Figure 10 21 The entire instructi...

Page 235: ...rnal bus is granted to another device The other device can release the bus by deasserting bus request Once the bus is released the ADSP 21xx deasserts BG and BGH and executes the external access Figure 10 22 shows timing for the BGH signal CLKOUT BR BG BR BG If a memory access is in progress BG is asserted in the cycle after the access is completed If no memory access is in progress BG is asserted...

Page 236: ...4 bit words of internal program memory RAM and 16K x 16 bit words of internal data memory RAM There are four separate memory spaces data memory program memory byte memory and I O memory To provide external access to these memory spaces the ADSP 2181 extends the internal address and data buses off chip and provides the PMS DMS BMS and IOMS select lines The PMS DMS BMS and IOMS signals indicate whic...

Page 237: ...D and WR remain high deasserted and the address and data buses are tristated Figure 10 23 ADSP 2181 System Diagram BR BG CLKIN IRQ2 ADSP 2181 1 2x CLOCK or CRYSTAL XTAL DR1 or FI SERIAL DEVICE DT1 or FO SCLK1 SPORT 1 RFS1 or IRQ0 TFS1 or IRQ1 DR0 DT0 TFS0 SCLK0 RFS0 SPORT 0 SERIAL DEVICE ADDR DATA PMS DMS ADDR13 0 DATA23 0 ADDR DATA A0 A21 DATA CS OVERLAY MEMORY Two 8K PM Segments Two 8K DM Segmen...

Page 238: ...nsfer to from internal memory in the background while continuing foreground processing For complete information on the BDMA port including booting and IDMA port refer to the DMA Ports chapter of this manual The ADSP 2181 uses a half instruction rate clock input from which it generates a full instruction rate internal clock For example from a 16 67 MHz clock input CLKIN the ADSP 2181 generates a 33...

Page 239: ...memory maps for program memory The program memory overlay select register PMOVLAY lets you choose a memory overlay to map from address PM 0x2000 to address PM 0x3FFF The memory mapped to this space and corresponding PMOVLAY register values are shown in Figure 10 25 Table 10 3 shows how PMOVLAY relates to the addressing of memory locations with address line A13 PMOVLAY Memory A13 A12 0 0 Internal 1...

Page 240: ... 3 instruction PMOVLAY is loaded with the contents of address DM 0x1234 PMOVLAY 2 type 7 instruction PMOVLAY is loaded with the value 2 PMOVLAY AX0 PMOVLAY is loaded from AX0 register AX0 PMOVLAY AX0 is loaded from PMOVLAY register If you are using a system design that sets MMAP 1 note that the first 8K is used to support a single segment of external memory This allows an external ROM based system...

Page 241: ...omposite Memory Select CMSSEL is configured to assert the CMS control line when Program Memory Select PMS or Data Memory Select DMS are asserted The order of overlays stored in this design from lowest address to highest is PM Overlay 1 PM Overlay 2 DM Overlay 1 and DM Overlay 2 Address line 13 A13 of the ADSP 2181 selects between overlay 1 or 2 Figure 10 27 shows a memory map of this design A14 A1...

Page 242: ...t PMOVLAY register value can result in program execution errors For example if your program is performing a loop operation on one of the external overlays and the program changes to another external or internal overlay an incorrect loop operation could occur The contents of the PMOVLAY register are not automatically saved and restored on the processors status stack when the processor responds to a...

Page 243: ...tatus registers are mapped into the top locations of internal data memory addresses 0x3FE0 0x3FFF Most of the ADSP 2181 s control registers correspond to those found on other ADSP 21xx processors Note that the ADSP 2181 s System Control Register does not have the boot memory control fields found on other ADSP 21xx processors Also note that the Waitstate Control Register Figure 10 29 ADSP 2181 Data...

Page 244: ... 0x0000 and 0x1FFF Table 10 4 DMOVLAY and Data Memory Overlay Addressing The following example instructions demonstrate how to use the DMOVLAY register DMOVLAY DM 0x1234 type 3 instruction DMOVLAY is loaded with the contents of address DM 0x1234 DMOVLAY 2 type 7 instruction DMOVLAY is loaded with the value 2 DMOVLAY AX0 DMOVLAY is loaded from AX0 register AX0 DMOVLAY AX0 is loaded from DMOVLAY reg...

Page 245: ...t LSB alignment Each read write to byte memory consists of data on data bus lines 15 8 and address on address bus lines 13 0 plus data lines 23 16 The 22 bit byte memory address lets you access up to 4M bytes of ROM or RAM For complete information on the ADSP 2181 s byte memory and BDMA port refer to the DMA Ports chapter of this manual 10 6 4 ADSP 2181 I O Memory Space The ADSP 2181 has a dedicat...

Page 246: ... waitstates 0 7 for accesses to I O memory addresses 0x400 0x5FF IOWAIT3 This 3 bit field sets the number of waitstates 0 7 for accesses to I O memory addresses 0x600 0x7FF DWAIT This 3 bit field sets the number of waitstates 0 7 for accesses to external program and data memory overlays Note The PWAIT field of the System Control Register sets the number of waitstates for access to external program...

Page 247: ...s I O memory peripherals and transfer the sample data using IDMA This combination of the I O memory and IDMA channels reduces system bus transfer rate limitations Note As with other ADSP 2100 Family processors on the ADSP 2181 you can define memory mapped I O ports with the assembler s PORT directive On the ADSP 2181 this directive defines memory mapped I O ports in external program memory overlay...

Page 248: ...elect signals PMS DMS BMS and IOMS Based on the value of CMSSEL in the Programmable Flag Composite Select Control register see Figure 10 33 the ADSP 2181 asserts CMS Figure 10 33 CMSSEL Selection for CMS CMS CMS CMS CMS Signal when the corresponding memory select signal or signals are asserted Each xMS signal can be individually enabled After reset CMSSEL is initialized to enable PMS DMS and IOMS ...

Page 249: ...in the following sequence see Figure 10 34 1 The ADSP 2181 executes a read from an external memory address the address is driven on the address bus and PMS DMS BMS or IOMS and RD is asserted CMS may also be asserted depending how it is configured 2 The external peripheral drives the data onto the data bus 3 The ADSP 2181 reads the data and deasserts RD WR remains high deasserted throughout the ext...

Page 250: ...OMS and WR is asserted CMS may also be asserted depending how it is configured 2 The external peripheral stores the data 3 The ADSP 2181 stops driving the address and data buses and deasserts WR Figure 10 35 External Memory Write Timing RD remains high deasserted throughout the external memory write operation 10 7 MEMORY INTERFACE SUMMARY ALL PROCESSORS Table 10 5 summarizes the states of the memo...

Page 251: ...for Boot page read address Table 10 5 Pin States During Memory Accesses Operation Address Data PMS RD CLKOUT SPORTs BG DMS WR BMS Reset tristated tristated high high active tristated high Booting active active BMS active RD active active tristated high after Reset PMS DMS WR high high BR Asserted tristated tristated tristated tristated active active low during Normal Operation Booting or Go Mode B...

Page 252: ...nd while continuing foreground processing These DMA transfers are accomplished internally by cycle stealing in the same way as serial port autobuffering This means that the ADSP 2181 uses internal bus cycles to transfer the data to and from memory The stolen cycles will only occur at instruction cycle boundaries i e not between cycles of a multiple cycle instruction See IACKAcknowledge DMA Cycle S...

Page 253: ...s on address bus lines 13 0 plus data lines 23 16 The 22 bit byte memory address lets you access up to 4M bytes of ROM or RAM BR BG CLKIN IRQ2 ADSP 2181 1 2x CLOCK or CRYSTAL XTAL DR1 or FI SERIAL DEVICE DT1 or FO SCLK1 SPORT 1 RFS1 or IRQ0 TFS1 or IRQ1 DR0 DT0 TFS0 SCLK0 RFS0 SPORT 0 SERIAL DEVICE ADDR DATA PMS DMS ADDR13 0 DATA23 0 ADDR DATA A0 A21 DATA CS OVERLAY MEMORY Two 8K PM Segments Two 8...

Page 254: ... doing BDMA accesses Note For more information on the ADSP 2100 Family Development Software Tools see the ADSP 2100 Family Assembler Tools Simulator Manual and current software release note When using BDMA for non boot loading transfers a BDMA transfer begins when data is written to the BWCOUNT register and a BDMA interrupt is issued when the transfer is complete The following restrictions apply t...

Page 255: ... 100 24 bit program memory words through the BDMA port assuming five waitstates and no hold offs the operation would take 1900 cycles This is shown in the following equation 100 3 5 1 1 0 PM Bytes Added Cycle Cycle for Hold Words per Waitstates for Internal Offs Word per Byte Transfer RD WR Hold offs for DMA transfers are defined in the section DMA Cycle Stealing DMA Hold Offs and IACKAcknowledge ...

Page 256: ...0 0 0 0 0 0 BDMA Internal Address 0 0 0 0 0 0 0 0 0 DM 0x3FE1 BIAD Figure 11 2 BDMA Internal Address Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 BDMA External Address 0 0 0 0 0 0 0 0 0 DM 0x3FE2 BEAD Figure 11 3 BDMA External Address Register ...

Page 257: ... Memory Space PM DM DM DM Word Size 24 16 8 8 Alignment full full MSB LSB word word Figure 11 4 BDMA Control Register The BDMA Control Register lets you set The BDMA Transfer Type BTYPE The BDMA Direction BDIR The BDMA Context Reset BCR The BDMA Page BMPAGE BTYPE can be 00 24 bit Program Memory Words 01 16 bit Data Memory 10 8 bit bytes for Data Memory MSB alignment 10 8 bit bytes for Data Memory ...

Page 258: ...or issues a BDMA interrupt When MMAP and BMODE are set to zero on boot a value of 32 decimal is written to this register directing the ADSP 2181 to load the first 32 locations of its internal program memory Two useful control techniques using this register are Poll the BWCOUNT register to determine when the DMA transfer is complete BWCOUNT 0 instead of waiting for the BDMA interrupt Abort the DMA ...

Page 259: ...10 9 8 7 6 5 4 3 2 1 0 BDMA Word Count MMAP 1 or BMODE 1 BWCOUNT DM 0x3FE4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 or 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMWAIT 1 0 1 1 1 1 0 Programmable Flag Composite Select Control PFTYPE 1 Output 0 Input 1 0 0 0 0 CMSSEL 1 Enable CMS 0 Disable CMS DM 0x3FE6 0 0 0 0 DM BM IOM PM Figure 11 6 BMWAIT Field in Programmable Flag Composite Select Control Register ...

Page 260: ...yte Memory Byte Memory Memory Address Memory BTYPE Address Contents page 0x00 Contents 00 PM 0x0000 0xABCDEF BM 0x0000 0xAB BM 0x0001 0xCD BM 0x0002 0xEF 00 PM 0x0001 0x123456 BM 0x0003 0x12 BM 0x0004 0x34 BM 0x0005 0x56 01 DM 0x0000 0x9876 BM 0x0006 0x98 BM 0x0007 0x76 01 DM 0x0001 0x3456 BM 0x0008 0x34 BM 0x0009 0x56 10 DM 0x0002 0x9800 BM 0x000A 0x98 10 DM 0x0003 0x7600 BM 0x000B 0x76 11 DM 0x0...

Page 261: ...ce after reset when the BMODE and MMAP pins are held low The BDMA port is initialized for booting as follows BWCOUNT is set to 32 BDIR BMPAGE BEAD BIAD and BTYPE are set to zero BCR is set to 1 BMWAIT is set to 7 These initializations set the BDMA port to load 32 words BWCOUNT from BDIR byte memory page zero BMPAGE byte memory address zero BEAD to internal Program Memory address zero BIAD using 24...

Page 262: ...curs At that point all of program memory is loaded 11 2 4 1 Development Software Features for BDMA Booting The ADSP 21xx PROM Splitter utility lets you create BDMA boot loader programs for ADSP 2181 based designs This provides a low overhead method for BDMA boot loading your program The boot loader program adds memory loader code to your executable program The PROM Splitter generates loader code t...

Page 263: ...increases throughput for block data transfers Through the IDMA port internal memory accesses can be performed with an overhead of one DSP processor cycle per word The ADSP 2181 supports boot loading through the IDMA port through the BDMA port or from an external Program Memory Overlay The BMODE and MMAP pins select the DSP s boot mode and memory map Setting BMODE 1 and MMAP 0 directs the ADSP 2181...

Page 264: ...he ADSP 2181 to write the input from the IDMA data bus to the address pointed to by the IDMA register When reading writing to Data Memory the IDMA data bus pins make up a 16 bit Data Memory word When reading writing to Program Memory the upper 16 bits of the 24 bit Program Memory word are sent first on the IDMA data bus pins On the next IDMA Port read write the lowest 8 bits of the Program Memory ...

Page 265: ...len cycle used to do the memory access The case shown in Figure 11 8 is not the only way to use the IDMA port Some variations on this scheme include After completing an IDMA port read write operation the host could change the IDMA internal memory address and start a new operation from a different starting address After latching an IDMA internal memory address the host could stop the operation and ...

Page 266: ...tions These hardware software design restrictions include If your design has both the host and ADSP 2181 writing to the IDMA Control Register do not let both write to this register at the same time the results of this are indeterminate Host reads of internal Program Memory take two IDMA reads for a 24 bit word through a 16 bit port If an IDMA address latch cycle or a ADSP 2181 write to the IDMA Co...

Page 267: ...the host processor to read and write these registers however in order to determine the ADSP 2181 s configuration and then change it To read the memory mapped control registers you must first transfer the contents of these locations to another area of internal RAM The following code segment shows a loop that performs this task const NUM_REG 32 var dm ram temp_array NUM_REG i0 temp_array l0 0 i1 0x3...

Page 268: ...g address and destination memory type DM or PM using the IDMA address latch cycle The address latch cycle shown in Figure 11 9 consists of the following steps 1 Host ensures that IACKline is low 2 Host asserts IAL and IS directing the ADSP 2181 to latch the IDMA starting address from the IAD15 0 address data bus into the IDMA Control Register 3 Host drives the starting address bits 0 13 and destin...

Page 269: ...the contents of the location pointed to by the IDMA address on the IAD15 0 address data bus 3 ADSP 2181 deasserts IACKline indicating the requested data is being fetched When the ADSP 2181 asserts the IACKline the requested data is driven on the IAD address data bus 4 Host detects the IACKline is now low and reads the data READ DATA from the IAD15 0 address data bus After reading the data the host...

Page 270: ...The best and worst case response times given above assume no system hold offs Hold offs for DMA transfers are defined in the section DMA Cycle Stealing DMA Hold Offs and IACK Acknowledge at the end of this chapter Warning If an IDMA address latch cycle or an ADSP 2181 write to the IDMA Control Register occurs after a first Program Memory read cycle 16 bits the IDMA port will lose the second half o...

Page 271: ...he host must do an initial dummy read to make the ADSP 2181 put the first data word PREVIOUS DATA on the IAD15 0 bus Note that IAL is low inactive and IWRis high inactive throughout the read operation The IDMA Short Read and Long Read cycles provide different alternatives for implementing your DMA transfers Short reads are useful for hosts that can handle the faster timing of these accesses while ...

Page 272: ...81 to write the data on the IAD15 0 address data bus to the location pointed to by the target IDMA address 3 ADSP 2181 deasserts the IACKline indicating it recognizes the IDMA write operation 4 Host drives the data on the IAD address data bus 5 ADSP 2181 asserts IACKline indicating it latched the data on the IAD15 0 address data bus 6 Host recognizes the IACKline is now low stops driving the data ...

Page 273: ...he IACKline after the second Program Memory write or all Data Memory writes until the internal memory write is complete and the IDMA port is ready for another transaction Warning Host IDMA write accesses to internal Program Memory take two IDMA port writes 24 bit word through a 16 bit port If an IDMA address latch cycle or a ADSP 2181 write to the IDMA Control register occurs after a first program...

Page 274: ...ess 3 ADSP 2181 deasserts IACKline high indicating it recognizes the IDMA write operation 4 Host drives the data on the IAD address data bus 5 Host deasserts IWRand IS after meeting the short write timing requirements ending the short write cycle 6 ADSP 2181 detects IWR and IS have gone high then latches the data on the IAD address data bus 7 Host stops driving the data on the IAD15 0 address data...

Page 275: ...r host needs the ADSP 2181 to signal that it has written the data use the IDMA long read cycle The short write lets your host hold data on the bus just until it is latched and then release the bus If you are using the ADSP 2181 in a multiprocessing environment using the short write is one way to avoid tying up the IAD15 0 data bus waiting for IACKsignal Short writes are also useful for hosts that ...

Page 276: ...not access memory These are DMA hold offs Bus Request If the ADSP 2181 is being held in Bus Request when it attempts an external access DM overlay PM overlay or I O memory space or if it is not in GO mode processor execution stops in the middle of the cycle and no instruction boundary is encountered Therefore the IDMA port cannot complete its internal memory access and IACKwill be held off Externa...

Page 277: ... ADSP 2181 target system IDMA transfers may be held off for periods of time Using the IACKsignal simplifies your system design by allowing you to ignore hold off conditions If you always wait for IACKto assert before accessing the IDMA port the DMA transfers will always operate properly You can ignore IACK however if you are sure that no hold offs occur in your system or if your IDMA accesses are ...

Page 278: ...STAT contains status flags from arithmetic operations and fields in the Wait State register control the number of wait states for different zones of external memory There are two types of accesses for registers Dedicated registers such as MX0 and IMASK can be read and written explicitly in assembly language For example MX0 1234 IMASK 0xF Memory mapped registers the System Control Register Wait Sta...

Page 279: ...e location pointed to by I0 Once the read is complete I0 is updated by M0 PM I4 M5 MR1 is an indirect program memory data write to the address pointed to by I4 with a post modify by M5 The instruction JUMP I4 is an example of an indirect jump 12 1 1 1 Always Initialize L Registers The ADSP 21xx processors allow two addressing modes for data memory accesses direct and register indirect Indirect add...

Page 280: ...anch capability DAG1 DAG2 SPORT 0 RX0 TX0 SPORT0 Control 0x3FFA 0x3FF9 0x3FF8 0x3FF7 Multichannel enables RX 31 16 RX 15 0 TX 31 16 TX 15 0 0x3FF6 0x3FF5 0x3FF4 0x3FF3 Control SCLKDIV RFSDIV Autobuffer RX1 TX1 SPORT 1 SPORT1 Control 0x3FF2 0x3FF1 0x3FF0 0x3FEF Control SCLKDIV RFSDIV Autobuffer TIMER TPERIOD TCOUNT TSCALE 0x3FFD 0x3FFC 0x3FFB IDMA PORT BDMA PORT PROGRAMMABLE FLAGS ADSP 2181 0x3FE0 ...

Page 281: ...all interrupts to be masked without changing the contents of the IMASK register Disabling interrupts does not affect serial port autobuffering which will operate normally whether or not interrupts are enabled The disable interrupt instruction masks all user interrupts including the powerdown interrupt The interrupt enable instruction allows all unmasked interrupts to be serviced again 12 1 2 2 Loo...

Page 282: ...ally pushed or popped using the PC Stack Control instructions TOPPCSTACK reg and reg TOPPCSTACK The loop stack is 18 bits wide 14 bits for the end of loop address and 4 bits for the termination condition code The loop stack is four locations deep It is automatically pushed during the execution of a DO UNTIL instruction It is popped automatically during a loop exit if the loop was nested The loop s...

Page 283: ...he SB register stores the block exponent for block floating point operations The SE register holds the shift value for normalize and denormalize operations Registers in the computational units have secondary registers shown in Figure 12 1 as second set of registers behind the first set Secondary registers are useful for single cycle context switches The selection of these secondary registers is co...

Page 284: ... and an internally generated serial clock RFSDIV is set to 255 for 256 SCLK cycles between RFS assertions SCLKDIV is set to 2 resulting in an SCLK frequency that is 1 6 of the CLKOUT frequency SI 0xB27 DM 0X3FF6 SI SPORT0 control register SI 2 DM 0x3FF5 SI SCLKDIV 2 SI 255 DM 0x3FF4 SI RFSDIV 255 12 1 7 Memory Interface SPORT Enables The System Control Register memory mapped at DM 0x3FFF contains ...

Page 285: ...has four memory mapped registers These registers are memory mapped in data memory locations 0x3FEC 0x3FEF The transmit register sends data to the DAC for transmitting The receive register receives data from the ADC The analog control register contains bits that select amplifier gain analog input and filter options 12 2 PROGRAM EXAMPLE Listing 12 1 presents an example of an FIR filter program writt...

Page 286: ...ff start CNTR data_buffer DO clear UNTIL CE clear data buffer clear DM I0 M0 0 set up memory mapped control registers AX0 191 DM 0x3FF4 AX0 set up divide value for 8KHz RFS AX0 3 DM 0x3FF5 AX0 1 536MHz internal serial clock AX0 0x69B7 DM 0x3FF6 AX0 multichannel disabled internally generated serial clock receive frame sync required receive width 0 transmit frame sync required transmit width 0 int t...

Page 287: ...is required Section C shows the setup of interrupts Since this code module is located at absolute address zero as indicated by the ABS qualifier in the MODULE directive the first instruction is placed at the restart vector address 0x0000 The first location is the restart vector instruction which jumps to the routine restarter Interrupt vectors that are not used are filled with a return from interr...

Page 288: ...ne N 1 passes within DO UNTIL SI RX0 read from SPORT0 DM I0 M0 SI transfer data to buffer MR 0 MY0 PM I4 M4 MX0 DM I0 M0 set up multiplier for loop DO convolution UNTIL CE CE counter expired convolution MR MR MX0 MY0 SS MY0 PM I4 M4 MX0 DM I0 M0 MAC these fetch next MR MR MX0 MY0 RND Nth pass with rounding TX0 MR1 write to sport RTI return from interrupt ENDMOD Listing 12 2 Interrupt Routine 12 2 ...

Page 289: ... PM I4 M4 MX0 DM I0 M0 zeroes the multiplier result register MR and fetches the first two operands This instruction accesses both program and data memory but still executes in a single cycle because of the processor s architecture The convolution label identifies the loop itself consisting of only two instructions one setting up the loop DO UNTIL and one inside the loop The MAC instruction multipl...

Page 290: ... to the ADSP 21xx serial ports host interface port HIP or the memory port As with any hardware design it is important that timing information be carefully analyzed Therefore the data sheet for the particular ADSP 2100 family processor used should be used in addition to the information presented in this chapter 13 1 ...

Page 291: ... described below This example shows a simple way to download programs from a host processor to the internal program memory of an ADSP 21xx There are several techniques for connecting a DSP processor to a host The choice of which technique to use depends upon the I O structure of the host availability of I O port lines and the amount of address decoding logic already available in the system Figure ...

Page 292: ... Hardware Examples 13 3 PB8 PB9 PB10 PB0 7 ADSP 21xx RESET BMS BR BG PR CLK D Q 74LS74 Q D8 15 Can Be Polled If Necessary VDD 5 kΩ 8 Host Microcontroller Port Bits Figure 13 1 ADSP 21xx Booting From Host ...

Page 293: ...ting the boot process Note that if PB8 is not low at power up the ADSP 21xx will start executing undefined instructions until PB8 is brought low The boot data is presented by the microcontroller either through 8 port bits PB0 7 or through a memory mapped port The PB0 7 bits should be put into a high impedance state after the boot is complete to prevent bus contention if the ADSP 21xx tries to writ...

Page 294: ...conversion digital to analog conversion and filtering in one device The codec shown in this example also performs pulse code modulation PCM encoding and decoding according to the CCITT µ law standard PCM compresses digital data so that fewer bits are needed to store the same information The ADSP 21xx serial ports have both µ law and A law companding compressing expanding capability In the example ...

Page 295: ...e master clocks for the receive and transmit sections of the codec respectively BCLKX is the bit clock and in this configuration is used for clocking both received and transmitted serial data MCLKR MCLKX and BCLKX must be synchronous and in this case they are the same signal namely the SCLK0 output generated by the ADSP 21xx processor The BCLKR CLKSEL input tied low selects the frequency of MCLKX ...

Page 296: ...mple Internally generated serial clock 2 048 MHz serial clock frequency Both transmit and receive frame syncs required Use normal framing for both transmit and receive Internally generated transmit and receive frame syncs Both frame syncs active high Word length of eight bits µ law companding This code assumes the processor operating at 12 288 MHz The code also sets up the processor to request dat...

Page 297: ...ort connection to the AD766 is shown in Figure 13 3 In this configuration the processor generates SCLK internally and provides it to the DAC Serial data is output from the DT pin to the DATA input of the DAC The TFS signal provides the DAC s LE input LE should go low on the clock cycle after the LSB sixteenth bit of a word is transmitted to latch the 16 bit word into the DAC To provide this timing...

Page 298: ...1 0 0 Data format right justify zero fill Internally generated TFS Alternate transmit framing Transmit framing required SCLK generated internally MSB LSB DT TFS Latches data into DAC MSB SCLK Figure 13 4 SPORT To AD766 DAC Timing The configuration of the SPORT control registers for this application is shown in Figure 13 5 Figure 13 5 SPORT To AD766 DAC Control Register Settings ...

Page 299: ...al word The serial port connection to the AD7872 is shown in Figure 13 6 The timer regulates sampling via the CONVST input at a constant frequency Instead of the timer an unused serial clock or flag output from the ADSP 21xx processor can be programmed to generate the CONVST signal The AD7872 generates SCLK internally and provides it to the processor With the CONTROL input held at 5 V the SCLK sig...

Page 300: ...lly generated RFS Alternate receive framing Receive framing required SCLK generated externally Figure 13 8 SPORT To AD7872 ADC Control Register Settings RFS is configured for the alternate framing mode externally generated with inverted active low logic The SPORT must also be programmed for external serial clock and a serial word length of 16 bits The configuration of the SPORT control register fo...

Page 301: ...em dependent SLEN system dependent SLEN system dependent ISCLK 1 ISCLK 0 TFSR 1 TFSR 1 RFSR 1 RFSR 1 IRFS 0 IRFS 0 ITFS 1 ITFS 1 RFSDIV don t care RFSDIV don t care TFSW1 RFSW1 TFSW2 RFSW2 system dependent INVRFS1 INVTFS1 INVRFS2 INVTFS2 system dependent Figure 13 9 Serial Port Interface Between Two ADSP 21xx Processors ADSP 21xx 1 RFS1 TFS1 DT1 DR1 SCLK1 SPORT1 ADSP 21xx 2 RFS0 TFS0 DT0 DR0 SCLK0...

Page 302: ...on Each SPORT will generate an interrupt when the autobuffer transfer is complete The description of autobuffering in the Serial Port chapter shows an example of the code for setting up autobuffering 13 7 80C51 INTERFACE TO HOST INTERFACE PORT The host interface port HIP on the ADSP 2111 ADSP 2171 and ADSP 21msp5x processors facilitates communication with a host microcomputer such as the Intel 80C...

Page 303: ... to latch the address so that the 8 bit data can then be transferred on the HAD0 7 lines The 80C51 asserts WRfor a write or RD for a read In this example the 80C51 reads and writes 8 bit data so the ADSP 2111 s HSIZE input is tied high Only the lower eight bits of each HIP register are used HMD0 is tied low because the 80C51 uses separate read and write strobes rather than a single Read Write line...

Page 304: ...les is described in greater detail in Digital Signal Processing Applications Using The ADSP 2100 Family Volume 1 available from Prentice Hall They are presented here to show some aspects of typical programs The FFT example is a complete program showing a subroutine that performs the FFT and a main calling program that initializes registers and calls the FFT subroutine as well as an auxiliary routi...

Page 305: ...lp in hardware prototyping The software development system includes several programs System Builder Assembler Linker PROM Splitter Simulators and C Compiler with Runtime Library These programs are described in detail in the ADSP 2100 Family Assembler Tools Simulator Manual ADSP 2100 Family C Tools Manual and ADSP 2100 Family C Runtime Library Manual Figure 14 1 shows a flow chart of the system dev...

Page 306: ...of assembly language comprising a main program subroutine or data variable declarations C programmers write C language files and use the C compiler to create assembly code modules from them Assembly language programmers write assembly code modules directly Each code module is assembled separately by the assembler The linker links several modules together to form an executable program memory image ...

Page 307: ...you can use an EZ ICE in circuit emulator in the prototype hardware to test circuitry timing and real time software execution The PROM splitter software tool translates the linker output program memory image file into an industry standard file format for a PROM programmer Once you program the code in PROM devices and install an ADSP 21xx processor into your prototype it is ready to run 14 3 SINGLE...

Page 308: ...ter coefficient table L4 Filter length N M1 M5 1 CNTR Filter length 1 N 1 Return Values MR1 Sum of products rounded and saturated I0 Oldest input data value in delay line I4 Beginning of filter coefficient table Altered Registers MX0 MY0 MR Computation Time N 1 5 2 cycles All coefficients and data values are assumed to be in 1 15 format ENTRY fir fir MR 0 MX0 DM I0 M1 MY0 PM I4 M5 DO sop UNTIL CE ...

Page 309: ...icient quantization and the recursive accumulation errors A subroutine that implements a high order filter is shown in Listing 14 2 A circular buffer in program memory contains the scaled biquad coefficients These coefficients are stored in the order B2 B1 B0 A2 and A1 for each biquad The individual biquad coefficient groups must be stored in the order that the biquads are cascaded MODULE biquad_s...

Page 310: ... MY0 SS MX1 DM I0 M0 MY0 PM I4 M4 MR MR MX1 MY0 SS MY0 PM I4 M4 MR MR SR1 MY0 SS MX0 DM I0 M0 MY0 PM I4 M4 MR MR MX0 MY0 SS MX0 DM I0 M1 MY0 PM I4 M4 DM I0 M0 MX1 MR MR MX0 MY0 RND sections DM I0 M0 SR1 SR ASHIFT MR1 HI DM I0 M0 MX0 DM I0 M3 SR1 RTS ENDMOD Listing 14 2 Cascaded Biquad IIR Filter 14 5 SINE APPROXIMATION The following formula approximates the sine of the input variable x sin x 3 140...

Page 311: ... 0x7FFF and 180 equals the maximum negative value 0x8000 The routine shown in Listing 14 3 first adjusts the input angle to its equivalent in the first quadrant The sine of the modified angle is calculated by multiplying increasing powers of the angle by the appropriate coefficients The result is adjusted if necessary to compensate for the modifications made to the original input value MODULE Sin_...

Page 312: ... PASS AX0 IF LT AR AR Negate output if needed RTS ENDMOD Listing 14 3 Sine Approximation 14 6 SINGLE PRECISION MATRIX MULTIPLY The routine presented in this section multiplies two input matrices X an RxS R rows S columns matrix stored in data memory and Y an SxT S rows T columns matrix stored in program memory The output Z an RxT R rows T columns matrix is written to data memory The routine is sho...

Page 313: ...SxT matrix Z is an RxT matrix Calling Parameters I1 Z buffer in data memory L1 0 I2 X stored by rows in data memory L2 0 I6 Y stored by rows in program memory L6 0 M0 1 M1 S M4 1 M5 T L0 L4 L5 0 SE Appropriate scale value CNTR R Return Values Z Buffer filled by rows Altered Registers I0 I1 I2 I4 I5 MR MX0 MY0 SR Computation Time S 8 T 4 R 2 2 cycles ...

Page 314: ... bit reversed address order so that the FFT output will be in the normal sequential order The next subroutine computes the FFT and the third scales the output data to maintain the block floating point data format The program is contained in four modules The main module declares and initializes data buffers and calls subroutines The other three modules contain the FFT bit reversal and block floatin...

Page 315: ...imag dat values initialize the twid_imag buffer that stores the sine values of the twiddle factors In an actual system the hardware would be set up to initialize these memory locations The variable called groups is initialized to N_div_2 and bflys_per_group and node_space are each initialized to 2 because there are two butterflies per group in the second stage of the FFT The blk_exponent variable ...

Page 316: ...broutine The radix 2 DIT FFT routine is shown in Listing 14 6 The constants N and log2N are the number of points and the number of stages in the FFT respectively To change the number of points in the FFT you modify these constants The first and last stages of the FFT are performed outside of the loop that executes all the other stages Treating the first and last stages individually allows them to ...

Page 317: ...real real FFT results sequential order inplaceimag imag FFT results sequential order Altered Registers I0 I1 I2 I3 I4 I5 L0 L1 L2 L3 L4 L5 M0 M1 M2 M3 M4 M5 AX0 AX1 AY0 AY1 AR AF MX0 MX1 MY0 MY1 MR SB SE SR SI Altered Memory inplacereal inplaceimag groups node_space bflys_per_group blk_exponent CONST log2N 10 N 1024 nover2 512 nover4 256 EXTERNAL twid_real twid_imag EXTERNAL inplacereal inplaceima...

Page 318: ...J AR DM I2 M2 AR AR AX1 AY1 AX0 DM I0 M0 SB EXPADJ AR DM I3 M2 AR AY0 DM I1 M0 group_lp AY1 DM I3 M0 CALL bfp_adj STAGES 2 TO N 1 DO stage_loop UNTIL CE Compute all stages in FFT I0 inplacereal I0 x0 in 1st grp of stage I2 inplaceimag I2 y0 in 1st grp of stage SI DM groups SR ASHIFT SI BY 1 LO groups 2 DM groups SR0 groups groups 2 CNTR SR0 CNTR group counter M4 SR0 M4 twiddle factor modifier M2 D...

Page 319: ...k for bit growth y1 y0 y1 C x1 S AR AX0 AY0 MX1 DM I3 M0 MY1 PM I5 M4 AR x0 x1 C y1 S MX1 next y1 MY1 next S SB EXPADJ AR DM I1 M1 AR Check for bit growth x1 x0 x1 C y1 S AR AX0 AY0 MX0 DM I1 M0 MY0 PM I4 M4 AR x0 x1 C y1 S MX0 next x1 MY0 next C SB EXPADJ AR DM I0 M1 AR Check for bit growth x0 x0 x1 C y1 S AR AX1 AY1 AR y0 y1 C x1 S bfly_loop SB EXPADJ AR DM I2 M1 AR Check for bit growth y0 y0 y1...

Page 320: ...SS AY1 y1 C x1 S MR x1 C MR MR MX1 MY1 RND MR x1 C y1 S AY0 MR1 AR AX1 AY1 AY0 x1 C y1 S AR y0 y1 C x1 S SB EXPADJ AR DM I3 M1 AR Check for bit growth y1 y0 y1 C x1 S AR AX0 AY0 MX1 DM I3 M0 MY1 PM I5 M4 AR x0 x1 C y1 S MX1 next y1 MY1 next S SB EXPADJ AR DM I1 M1 AR Check for bit growth x1 x0 x1 C y1 S AR AX0 AY0 MX0 DM I1 M0 MY0 PM I4 M4 AR x0 x1 C y1 S MX0 next x1 MY0 next C SB EXPADJ AR DM I0 ...

Page 321: ...placereal Altered Registers I0 I4 M0 M4 AY1 Altered Memory inplacereal CONST N 1024 mod_value H 0010 Initialize constants EXTERNAL inputreal inplacereal ENTRY scramble scramble I4 inputreal I4 sequentially ordered data I0 inplacereal I0 scrambled data M4 1 M0 mod_value M0 modifier for reversing N bits L4 0 L0 0 CNTR N ENA BIT_REV Enable bit reversed outputs on DAG1 DO brev UNTIL CE AY1 DM I4 M4 Re...

Page 322: ... 2 DIT FFT stage results in inplacereal and inplaceimag Return Parameters inplacereal and inplaceimag adjusted for bit growth Altered Registers I0 I1 AX0 AY0 AR MX0 MY0 MR CNTR Altered Memory inplacereal inplaceimag blk_exponent CONST Ntimes2 2048 EXTERNAL inplacereal blk_exponent Begin declaration section ENTRY bfp_adj bfp_adj AY0 CNTR Check for last stage AR AY0 1 IF EQ RTS If last stage return ...

Page 323: ..._shift CNTR Ntimes2 1 initialize loop counter DO shift_loop UNTIL CE Shift block of data MR MX0 MY0 RND MX0 DM I0 M1 MR shifted data MX0 next value shift_loop DM I1 M1 MR1 Unshifted data shifted data MR MX0 MY0 RND Shift last data word AY0 DM blk_exponent Update block exponent and DM I1 M1 MR1 AR AY0 AX0 store last shifted sample DM blk_exponent AR RTS ENDMOD Listing 14 8 Radix 2 Block Floating Po...

Page 324: ...Logical Shift p 15 52 Normalize p 15 54 Derive Exponent p 15 56 Block Exponent Adjust p 15 58 Arithmetic Shift Immediate p 15 60 Logical Shift Immediate p 15 62 MOVE Register Move p 15 63 Load Register Immediate p 15 65 Data Memory Read Direct Address p 15 67 Data Memory Read Indirect Address p 15 68 Program Memory Read Indirect Address p 15 69 Data Memory Write Direct Address p 15 70 Data Memory ...

Page 325: ...perations are available The high level syntax of ADSP 2100 family source code is both readable and efficient Unlike many assembly languages the ADSP 2100 family instruction set uses an algebraic notation for arithmetic operations and for data moves resulting in highly readable source code There is no performance penalty for this each program statement assembles into one 24 bit instruction which ex...

Page 326: ...a register move to or from either internal or external memory 15 3 INSTRUCTION TYPES NOTATION CONVENTIONS The ADSP 2100 family instruction set is grouped into the following categories Computational ALU MAC Shifter Move Program Flow Multifunction Miscellaneous Because the multifunction instructions best illustrate the power of the processors architecture in the next section we begin with a discussi...

Page 327: ...es an immediate address value to be encoded in the instruction The addr may be either an immediate value a constant or a program label reg Refers to any accessible register see Table 15 7 dreg Refers to any data register see Table 15 7 Immediate values exp data or addr may be a constant in decimal hexadecimal octal or binary format Default is to decimal 15 4 MULTIFUNCTION INSTRUCTIONS Multifunctio...

Page 328: ...ance Note that indirect memory addressing uses a syntax similar to array indexing with DAG registers providing the index values Any I register may be paired with any M register within the same DAG As discussed in Chapter 2 Computational Units registers are read at the beginning of the cycle and written at the end of the cycle The operands present in the MX0 and MY0 registers at the beginning of th...

Page 329: ...tion instruction is AR AX0 AY0 AX0 DM I0 M3 Here an addition is performed in the ALU while a single operand is fetched from data memory The restrictions are similar to those for previous multifunction instructions The value of AX0 used as a source for the computation is the value at the beginning of the cycle The data read operation loads a new value into AX0 by the end of the cycle For this same ...

Page 330: ... MR2 As before the value of AX0 at the beginning of the instruction is the value used in the computation The move may be from or to all ALU MAC and Shifter input and output registers except the feedback registers AF and MF and SB In the example the data register move loads the AX0 register with the new value at the end of the cycle All ALU operations except division all MAC operations and all Shif...

Page 331: ...I5 M5 I6 M6 I7 M7 PM I4 M4 I5 M5 I6 M6 I7 M7 DM I0 M0 dreg ALU I1 M1 MAC I2 M2 SHIFT I3 M3 I4 M4 I5 M5 I6 M6 I7 M7 PM I4 M4 I5 M5 I6 M6 I7 M7 ALU dreg dreg MAC SHIFT Table 15 2 Multifunction Instructions ALU Any ALU instruction except DIVS DIVQ MAC Any multiply accumulate instruction SHIFT Any shifter instruction except Shift Immediate May not be conditional instruction AR MR result registers must...

Page 332: ...X0 AY0 C means that the ALU result register AR gets the value of the ALU X input and Y input registers plus the value of the carry in bit Table 15 3 gives a summary list of all ALU instructions In this list condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the ALU The conditional clause is optional and is ...

Page 333: ...ne of the MAC instructions Multiply Accumulate IF NOT MV MR MR MX0 MY0 UU The conditional expression IF NOT MV tests the MAC overflow bit If the condition is not true a NOP is executed The expression MR MR MX0 MY0 is the multiply accumulate operation the multiplier result register MR gets the value of itself plus the product of the X and Y input registers selected The modifier in parentheses UU tr...

Page 334: ...R 0 MF IF condition MR MR RND MF IF MV SAT MR Table 15 4 MAC Instructions 15 5 3 Shifter Group Here is an example of one of the Shifter instructions Normalize IF NOT CE SR SR OR NORM SI HI The conditional expression IF NOT CE tests the not counter expired condition If the condition is false a NOP is executed The destination of all shifting operations is the Shifter Result register SR The destinati...

Page 335: ...n SR SR OR LSHIFT xop HI LO IF condition SR SR OR NORM xop HI LO IF condition SE EXP xop HI LO HIX IF condition SB EXPADJ xop SR SR OR ASHIFT xop BY exp HI LO SR SR OR LSHIFT xop BY exp HI LO Table 15 5 Shifter Instructions 15 6 MOVE READ WRITE MOVE instructions shown in Table 15 6 move data to and from data registers and external memory Registers are divided into two groups referred to as reg whi...

Page 336: ...eg reg reg DM address dreg DM I0 M0 I1 M1 I2 M2 I3 M3 I4 M4 I5 M5 I6 M6 I7 M7 DM I0 M0 dreg I1 M1 data I2 M2 I3 M3 I4 M4 I5 M5 I6 M6 I7 M7 DM address reg reg data dreg PM I4 M4 I5 M5 I6 M6 I7 M7 PM I4 M4 dreg I5 M5 I6 M6 I7 M7 Table 15 6 MOVE Instructions ...

Page 337: ... point for routines outside the module Conversely the EXTERNAL directive makes it possible to use a label declared in another module If the counter condition CE NOT CE is to be used an assignment to CNTR must be executed to initialize the counter value JUMP and CALL permit the additional conditionals FLAG_IN and NOT FLAG_IN to be used for branching on the state of the FI pin but only with direct a...

Page 338: ... AZ 1 NE Not Equal Zero AZ 0 LT Less Than Zero AN XOR AV 1 GE Greater Than or Equal Zero AN XOR AV 0 LE Less Than or Equal Zero AN XOR AV OR AZ 1 GT Greater Than Zero AN XOR AV OR AZ 0 AC ALU Carry AC 1 NOT AC Not ALU Carry AC 0 AV ALU Overflow AV 1 NOT AV Not ALU Overflow AV 0 MV MAC Overflow MV 1 NOT MV Not MAC Overflow MV 0 NEG X Input Sign Negative AS 1 POS X Input Sign Positive AS 0 NOT CE No...

Page 339: ...nal or integer arithmetic and timer enabling A single ENA or DIS can be followed by any number of mode identifiers separated by commas ENA and DIS can also be repeated All seven modes can be enabled disabled or changed in a single instruction The MODIFY instruction modifies the address pointer in the I register selected with the value in the selected M register without performing any actual memory...

Page 340: ...s NOP PUSH STS POP CNTR POP PC POP LOOP POP ENA BIT_REV DIS AV_LATCH AR_SAT SEC_REG G_MODE M_MODE TIMER MODIFY I0 M0 I1 M1 I2 M2 I3 M3 I4 M4 I5 M5 I6 M6 I7 M7 IF condition SET FLAG_OUT RESET FL0 TOGGLE FL1 FL2 ENA INTS DIS Table 15 10 Miscellaneous Instructions ...

Page 341: ...ng as only one of the fetches is from external memory Two fetches must be from on chip memory either PM or DM 15 9 2 Wait States All family processors allow the programming of wait states for external memory chips Up to seven extra wait state cycles may be added to the processor s access time for external memory Extra cycles inserted due to wait states are in addition to any caused by multiple off...

Page 342: ... Example A One multifunction instruction AX0 DM I0 M0 a comma is used in multifunction instructions AY0 PM I4 M4 Example B Two separate instructions AX0 DM I0 M0 a semicolon terminates an instruction AY0 PM I4 M4 15 10 2 Syntax Notation Example Here is an example of one instruction the ALU Add Add with Carry instruction IF cond AR xop yop AF C yop C The permissible conds xops and yops are given in...

Page 343: ...gisters An asterisk indicates a bit in the status word that is changed by the execution of the instruction A dash indicates that a bit is not affected by the instruction 0 or 1 Indicates that a bit is unconditionally cleared or set For example the status word ASTAT is shown below ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 Here the MV bit is updated and the AV bit is cleared ...

Page 344: ...ion performs the addition unconditionally The addition operation adds the first source operand to the second source operand along with the ALU carry bit AC if designated by the C notation using binary addition The result is stored in the destination register The operands are contained in the data registers or constant specified in the instruction The xop constant operation is only available on the...

Page 345: ...th yop 0 Z Destination register Yop Y operand Xop X operand COND condition xop constant Conditional ALU MAC operation Instruction Type 9 ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case AMF 10010 for xop constant C AMF 10011 for xop constant Z Destination regi...

Page 346: ...on unconditionally The subtraction operation subtracts the second source operand from the first source operand and optionally adds the ALU Carry bit AC minus 1 H 0001 and stores the result in the destination register The C 1 quantity effectively implements a borrow capability for multiprecision subtractions The operands are contained in the data registers or constant specified in the instruction T...

Page 347: ...p yop operation Note that xop C 1 is a special case of xop yop C 1 with yop 0 Z Destination register Yop Y operand Xop X operand COND condition xop constant Conditional ALU MAC operation Instruction Type 9 ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case AMF 1...

Page 348: ...ot true then perform a no operation Omitting the condition performs the subtraction unconditionally The subtraction operation subtracts the second source operand from the first source operand optionally adds the ALU Carry bit AC minus 1 H 0001 and stores the result in the destination register The C 1 quantity effectively implements a borrow capability for multiprecision subtractions The operands a...

Page 349: ... yop xop C 1 AMF 11001 for yop xop Note that xop C 1 is a special case of yop xop C 1 with yop 0 Z Destination register Yop Y operand Xop X operand COND condition xop constant Conditional ALU MAC operation Instruction Type 9 ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation...

Page 350: ... perform the specified bitwise logical operation logical AND inclusive OR or exclusive OR If the condition is not true then perform a no operation Omitting the condition performs the logical operation unconditionally The operands are contained in the data registers or constant specified in the instruction The xop AND OR XOR constant operation is only available on the ADSP 217x ADSP 218x and ADSP 2...

Page 351: ...gister Yop Y operand Xop X operand COND condition xop AND OR XOR constant Conditional ALU MAC operation Instruction Type 9 ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case AMF 11100 for AND operation AMF 11101 for OR operation AMF 11110 for XOR operation Z Des...

Page 352: ... is not true then perform a no operation Omitting the condition performs the operation unconditionally These operations cannot be used in multifunction instructions These operations are defined as follows TSTBIT is an AND operation with a 1 in the selected bit SETBIT is an OR operation with a 1 in the selected bit CLRBIT is an AND operation with a 0 in the selected bit TGLBIT is an XOR operation w...

Page 353: ...struction Type 9 ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case AMF 11100 for AND operation AMF 11101 for OR operation AMF 11110 for XOR operation Z Destination register COND condition Xop X operand ALU TEST BIT SET BIT CLEAR BIT TOGGLE BIT ADSP 217x ADSP 21...

Page 354: ...93 8194 16384 16385 16386 32767 32768 Examples IF GE AR PASS AY0 AR PASS 0 AR PASS 8191 ADSP 217x ADSP 218x ADSP 21msp58 59 only Description Test the optional condition and if true pass the source operand unmodified through the ALU block and store in the destination register If the condition is not true perform a no operation Omitting the condition performs the PASS unconditionally The source oper...

Page 355: ...11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation In this case AMF 10000 for PASS yop AMF 10011 for PASS xop AMF 10001 for PASS 1 AMF 11000 for PASS 1 Note that PASS xop is a special case of xop yop with yop 0 Note that PASS 1 is a special case of yop 1 with yop 0 Note that PASS 1 is a special case of yop 1 with yop 0 Z Destination register Yop Y...

Page 356: ...orm a no operation Omitting the condition performs the NEGATE operation unconditionally The source operand is contained in the data register specified in the instruction Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if operand H 8000 Cleared otherwise AC Set if operand equa...

Page 357: ...store in the destination location If the condition is not true then perform a no operation Omitting the condition performs the complement operation unconditionally The source operand is contained in the data register specified in the instruction Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 0 AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cle...

Page 358: ...Omitting the condition performs the absolute value operation unconditionally The source operand is contained in the data register specified in the instruction Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 AZ Set if the result equals zero Cleared otherwise AN Set if xop is H 8000 Cleared otherwise AV Set if xop is H 8000 Cleared otherwise AC Always cleared AS Set if the source op...

Page 359: ...nditionally The source operand is contained in the data register specified in the instruction Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise Instruction Format Conditional ALU MAC ...

Page 360: ...ion unconditionally The source operand is contained in the data register specified in the instruction Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise Instruction Format Conditional ...

Page 361: ...y permissible xop The divide operation is then executed with the divide primitives DIVS and DIVQ Repeated execution of DIVQ implements a non restoring conditional add subtract division algorithm At the conclusion of the divide operation the quotient will be in AY0 To implement a signed divide first execute the DIVS instruction once which computes the sign of the quotient Then execute the DIVQ inst...

Page 362: ...ision Exceptions appendix of this manual Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AQ Loaded with the bit value equal to the AQ bit computed on each cycle from execution of the DIVS or DIVQ instruction Instruction Format DIVQ Instruction Type 23 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Xop 0 0 0 0 0 0 0 0 DIVS Instruction Type 24 ...

Page 363: ...t SUBTRACT Y X xop constant AND OR XOR xop constant PASS PASS constant using any constant other than 1 0 or 1 TSTBIT SETBIT CLRBIT TGLBIT Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an arithmetic overflow occurs Cleared otherwise AC Set if a carry is generated Cleared ...

Page 364: ...x and ADSP 21msp58 59 processors Both xops must be the same register This option allows single cycle X2 and X2 instructions The data format selection field following the two operands specifies whether each respective operand is in Signed S or Unsigned U format The xop is specified first and yop is second If the xop xop operation is used the data format selection field must be UU SS or RND only The...

Page 365: ...s case AMF FUNCTION Data Format X Operand Y Operand 0 0 1 0 0 xop yop SS Signed Signed 0 0 1 0 1 xop yop SU Signed Unsigned 0 0 1 1 0 xop yop US Unsigned Signed 0 0 1 1 1 xop yop UU Unsigned Unsigned 0 0 0 0 1 xop yop RND Signed Signed Z Destination register Yop Y operand register Xop X operand register COND condition xop xop Conditional ALU MAC Operation Instruction Type 9 ADSP 217x ADSP 218x ADS...

Page 366: ...ored in MF The xop xop squaring operation is only available on the ADSP 217x ADSP 218x and ADSP 21msp58 59 processors Both xops must be the same register This option allows single cycle X2 and X2 instructions The data format selection field to the right of the two operands specifies whether each respective operand is in signed S or unsigned U format The xop is specified first and yop is second If ...

Page 367: ... 0 COND AMF Specifies the ALU or MAC Operation In this case AMF FUNCTION Data Format X Operand Y Operand 0 1 0 0 0 MR xop yop SS Signed Signed 0 1 0 0 1 MR xop yop SU Signed Unsigned 0 1 0 1 0 MR xop yop US Unsigned Signed 0 1 0 1 1 MR xop yop UU Unsigned Unsigned 0 0 0 1 0 MR xop yop RND Signed Signed Z Destination register Yop Y operand register Xop X operand register COND condition xop xop Cond...

Page 368: ...n operand only bits 16 31 of the 40 bit result are stored in MF The xop xop squaring operation is only available on the ADSP 217x ADSP 218x and ADSP 21msp58 59 processors Both xops must be the same register The data format selection field to the right of the two operands specifies whether each respective operand is in signed S or unsigned U format The xop is specified first and yop is second If th...

Page 369: ...0 0 0 COND AMF Specifies the ALU or MAC Operation In this case AMF FUNCTION Data Format X Operand Y Operand 0 1 1 0 0 MR xop yop SS Signed Signed 0 1 1 0 1 MR xop yop SU Signed Unsigned 0 1 1 1 0 MR xop yop US Unsigned Signed 0 1 1 1 1 MR xop yop UU Unsigned Unsigned 0 0 0 1 1 MR xop yop RND Signed Signed Z Destination register Yop Y operand register Xop X operand register COND condition xop xop C...

Page 370: ...condition is not true perform a no operation Omitting the condition performs the clear unconditionally The entire 40 bit MR or 16 bit MF register is cleared to zero Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 MV Always cleared Instruction Format Conditional ALU MAC Operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 1 1 0 ...

Page 371: ...ulate specifying yop 0 as a multiplicand and adding the zero product to the contents of MR The MR register may be optionally rounded at the boundary between bits 15 and 16 of the result by specifying the RND option If MF is specified as the destination bits 31 16 of the result are stored in MF If MR is the destination the entire 40 bit result is stored in MR Status Generated ASTAT 7 6 5 4 3 2 1 0 ...

Page 372: ...tion instruction is intended to be used at the completion of a series of multiply accumulate operations so that temporary overflows do not cause the accumulator to saturate The saturation result depends on the state of MV and on the sign of MR the MSB of MR2 The possible results after execution of the saturation instruction are shown in the table below MV MSB of MR2 MR contents after saturation 0 ...

Page 373: ... the present contents of the SR register by selecting the SR OR option For ASHIFT with a positive Shift Code i e positive value in SE the operand is shifted left with a negative Shift Code i e negative value in SE the operand is shifted right The number of positions shifted is the count in the Shift Code The 32 bit output field is sign extended to the left the MSB of the input is replicated to the...

Page 374: ...hift Operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 SF Xop 0 0 0 0 COND SF Shifter Function 0 1 0 0 ASHIFT HI 0 1 0 1 ASHIFT HI OR 0 1 1 0 ASHIFT LO 0 1 1 1 ASHIFT LO OR Xop shifter operand COND condition ...

Page 375: ...e lower half LO option The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option For LSHIFT with a positive Shift Code the operand is shifted left the numbers of positions shifted is the count in the Shift Code The 32 bit output field is zero filled from the right Bits shifted out of the high order bit in the 32 bit destination field SR31 are...

Page 376: ...ift Operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 SF Xop 0 0 0 0 COND SF Shifter Function 0 0 0 0 LSHIFT HI 0 0 0 1 LSHIFT HI OR 0 0 1 0 LSHIFT LO 0 0 1 1 LSHIFT LO OR Xop shifter operand COND condition ...

Page 377: ...eferenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option When the LO reference is selected the 32 bit output field is zero filled to the left Bits shifted out of the high order bit in the 32 bit destination field SR31 are dropped The 32 bit output field ...

Page 378: ...struction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 SF Xop 0 0 0 0 COND SF Shifter Function 1 0 0 0 NORM HI 1 0 0 1 NORM HI OR 1 0 1 0 NORM LO 1 0 1 1 NORM LO OR Xop shifter operand COND condition SHIFTER NORMALIZE ...

Page 379: ...effective exponent of the input value The Shift Code depends on which exponent detector mode is used HI HIX LO In the HI mode the input is interpreted as a single precision signed number or as the upper half of a double precision signed number The exponent detector counts the number of leading sign bits in the source operand and stores the resulting Shift Code in SE The Shift Code will equal the n...

Page 380: ...lf was all sign bits then EXP in the LO mode totals the number of leading sign bits in the double precision word and stores the resulting Shift Code in SE Status Generated ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ SS Set by the MSB of the input for an EXP operation in the HI or HIX mode with AV 0 Set by the MSB inverted in the HIX mode with AV 1 Not affected by operations in the LO mode Instru...

Page 381: ...ut must be a signed twos complement number The exponent detector operates in HI mode see the EXP instruction above At the start of a block the SB register should be initialized to 16 to set SB to its minimum value On each execution of the EXPADJ instruction the effective exponent of each operand is compared to the current contents of the SB register If the new exponent is greater than the current ...

Page 382: ...EXPONENT ADJUST Instruction Format Conditional Shift Operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 SF Xop 0 0 0 0 COND SF 1111 Xop shifter operand COND condition ...

Page 383: ...tion For ASHIFT with a positive shift constant the operand is shifted left with a negative shift constant the operand is shifted right The 32 bit output field is sign extended to the left the MSB of the input is replicated to the left and the output is zero filled from the right Bits shifted out of the high order bit in the 32 bit destination field SR31 are dropped Bits shifted out of the low orde...

Page 384: ...5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 SF Xop exp SF Shifter Function 0 1 0 0 ASHIFT HI 0 1 0 1 ASHIFT HI OR 0 1 1 0 ASHIFT LO 0 1 1 1 ASHIFT LO OR Xop Shifter Operand exp 8 bit signed shift value SHIFTER ARITHMETIC SHIFT IMMEDIATE ...

Page 385: ...d to the left and from the right Bits shifted out of the high order bit in the 32 bit destination field SR31 are dropped For LSHIFT with a negative shift constant the operand is shifted right The 32 bit output field is zero filled from the left and to the right Bits shifted out of the low order bit are dropped To shift a double precision number the same shift constant is used for both parts of the...

Page 386: ... either sign extended to the left if the source is a signed value or zero filled to the left if the source is an unsigned value The unsigned registers which when used as the source cause the value stored in the destination to be zero filled to the left are I0 through I7 L0 through L7 CNTR PX ASTAT MSTAT SSTAT IMASK and ICNTL All other registers cause sign extension to the left When transferring a ...

Page 387: ...ST SRC DEST SOURCE RGP RGP REG REG SRC RGP Source Register Group and SOURCE REG Source Register select the source register according to the Register Selection Table see Appendix A DST RGP Destination Register Group and DEST REG Destination Register select the destination register according to the Register Selection Table see Appendix A MOVE REGISTER MOVE ...

Page 388: ...with 16 bits for data register loads and up to 14 bits for other register loads The value is always right justified in the destination location after the load bit 0 maps to bit 0 When a value of length less than the length of the destination is moved it is sign extended to the left to fill the destination width Note that whenever MR1 is loaded with data it is sign extended into MR2 For this instru...

Page 389: ... immediate data value One of the 16 Data Registers is selected according to the DREG Selection Table see Appendix A Load Non Data Register Immediate Instruction Type 7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 RGP DATA REG DATA contains the immediate value to be loaded into the Non Data Register destination location The data is right justified in the field so the value ...

Page 390: ... stored directly in the instruction word as a full 14 bit field The contents of the source are always right justified in the destination register after the read bit 0 maps to bit 0 Note that whenever MR1 is loaded with data it is sign extended into MR2 Status Generated None affected Instruction Format Data Memory Read Direct Address Instruction Type 3 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ...

Page 391: ...atus Generated None affected Instruction Format ALU MAC Operation with Data Memory Read Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 G 0 0 AMF 0 0 0 0 0 DREG I M AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Read In this case AMF 00000 indicating a no operation for the ALU MAC function DREG selects the destination ...

Page 392: ...stination register right justification If the destination register is less than 16 bits wide the most significant bits are dropped Bits PMD7 0 are always loaded into the PX register You may ignore these bits or read them out on a subsequent cycle Status Generated None affected Instruction Format ALU MAC Operation with Program Memory Read Instruction Type 5 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 393: ...a signed value or zero filled to the left if the source is an unsigned value The unsigned registers which are zero filled to the left are I0 through I7 L0 through L7 CNTR PX ASTAT MSTAT SSTAT IMASK and ICNTL All other registers are sign extended to the left The contents of the source are always right justified in the destination location after the write bit 0 maps to bit 0 Note that whenever MR1 i...

Page 394: ...ant or any symbol referenced with the length of or pointer to operators The addressing mode is register indirect with post modify For linear i e non circular indirect addressing the L register corresponding to the I register used must be set to zero When a register of less than 16 bits is written to memory the value written is sign extended to form a 16 bit value The contents of the source are alw...

Page 395: ...ration to be performed in parallel with the Data Memory Write In this case AMF 00000 indicating a no operation for the ALU MAC function Data represents the actual 16 bit value DREG selects the source Data Register One of the 16 Data Registers is selected according to the Register Selection Table see Appendix A G specifies which Data Address Generator the I and M registers are selected from These r...

Page 396: ...s of the Program Memory Data bus PMD7 0 are loaded from the PX register Whenever a source register of length less than 16 bits is written to memory the value written is sign extended to form a 16 bit value Status Generated None affected Instruction Format ALU MAC Operation with Program Memory Write Instruction Type 5 see Appendix A as shown below 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 397: ...y space These instructions move data between the processor data registers and the I O memory space Status Generated None affected Instruction Format I O Memory Space Read Write Instruction Type 29 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 D ADDR DREG ADDR contains the 11 bit direct address of the source or destination location in I O Memory Space DREG selects th...

Page 398: ...stored directly in the instruction word as a full 14 bit field For register indirect jumps the selected I register provides the address it is not post modified in this case If JUMP is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled If NOT CE is used as the condition execution of the JUMP instruction decrements the processor s counter CNTR regis...

Page 399: ...t or register indirect For direct addressing using an immediate address value or a label the program address is stored directly in the instruction word as a full 14 bit field For register indirect jumps the selected I register provides the address it is not post modified in this case If CALL is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled St...

Page 400: ...PC stack with the return address and causes program execution to continue at the address specified by the instruction The addressing mode for the CALL on FI must be direct If JUMP or CALL is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled For direct addressing using an immediate address value or a label the program address is stored directly in...

Page 401: ...tly alter the flow of your program it is provided to signal external devices Note that the FO pin is specified by FLAG_OUT in the instruction syntax The following table shows which flag outputs are present on each ADSP 21xx processor processor flag pin s ADSP 2101 FO ADSP 2105 FO ADSP 2115 FO ADSP 2111 FO FL0 FL1 FL2 ADSP 217x FO FL0 FL1 FL2 ADSP 218x FO FL0 FL1 FL2 ADSP 21msp5x FO FL0 FL1 FL2 Sta...

Page 402: ...s the return unconditionally RTS executes a program return from a subroutine The address on top of the PC stack is popped and is used as the return address The PC stack is the only stack popped If RTS is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled Status Generated None affected Instruction Field Conditional Return Instruction Type 20 23 22 ...

Page 403: ...rom an interrupt service routine The address on top of the PC stack is popped and is used as the return address The value on top of the status stack is also popped and is loaded into the arithmetic status ASTAT mode status MSTAT and the interrupt mask IMASK registers If RTI is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled Status Generated Non...

Page 404: ...rocessor s counter CNTR register is decremented once for each pass through the loop When the DO instruction is executed the address of the last instruction is pushed onto the loop stack along with the termination condition and the current program counter value plus 1 is pushed onto the PC stack Any nesting of DO loops continues the process of pushing the loop and PC stacks up to the limit of the l...

Page 405: ...on as shown below TERM Syntax Condition Tested 0 0 0 0 NE Not Equal to Zero 0 0 0 1 EQ Equal Zero 0 0 1 0 LE Less Than or Equal to Zero 0 0 1 1 GT Greater Than Zero 0 1 0 0 GE Greater Than or Equal to Zero 0 1 0 1 LT Less Than Zero 0 1 1 0 NOT AV Not ALU Overflow 0 1 1 1 AV ALU Overflow 1 0 0 0 NOT AC Not ALU Carry 1 0 0 1 AC ALU Carry 1 0 1 0 POS X Input Sign Positive 1 0 1 1 NEG X Input Sign Neg...

Page 406: ...ced by the same ratio When the IDLE n instruction is used it slows the processor s internal clock and thus its response time to incoming interrupts the 1 cycle response time of the standard IDLE state is increased by n the clock divisor When an enabled interrupt is received the ADSP 21xx will remain in the IDLE state for up to a maximum of n CLKIN cycles where n 16 32 64 or 128 before resuming nor...

Page 407: ...cally whenever an interrupt service routine is entered Any POP pops the value on the top of the designated stack and decrements the same stack pointer to point to the next lowest location in the stack POP STS causes the arithmetic status ASTAT mode status MSTAT and interrupt mask IMASK to be popped into these same registers This also happens automatically whenever a return from interrupt RTI is ex...

Page 408: ...orrectly There is no standard PUSH PC stack instruction To push a specific value onto the PC stack therefore use the following special instruction TOPPCSTACK reg push reg contents onto PC stack The stack is pushed immediately in the same cycle Note that TOPPCSTACK may not be used as a register in any other instruction type Examples AX0 TOPPCSTACK pop PC stack into AX0 NOP TOPPCSTACK I7 push conten...

Page 409: ...oup and SOURCE REG Source Register select the source register according to the Register Selection Table see Appendix A reg TOPPCSTACK Internal Data Move Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 0 0 DST 1 1 DEST 1 1 1 1 RGP REG DST RGP Destination Register Group and DEST REG Destination Register select the destination register according t...

Page 410: ...tch Mode 3 AR_SAT ALU AR Register Saturation Mode 4 M_MODE MAC Result Placement Mode 5 TIMER Timer Enable 6 G_MODE Enables GO Mode The data register bank select bit SEC_REG determines which set of data registers is currently active 0 primary 1 secondary The bit reverse mode bit BIT_REV when set to 1 causes addresses generated by Data Address Generator 1 to be output in bit reversed order The ALU o...

Page 411: ...ode G_MODE allows an ADSP 21xx processor to continue executing instructions from internal memory if possible during a bus grant The GO mode allows the processor to run only if an external memory access is required does the processor halt waiting for the bus to be released Instruction Format Mode Control Instruction Type 18 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0...

Page 412: ...er used must be set to zero The selection of the I and M registers is constrained to registers within the same Data Address Generator selection of I0 I3 in Data Address Generator 1 constrains selection of the M registers to M0 M3 Similarly selection of I4 I7 constrains the M registers to M4 M7 Status Generated None affected Instruction Format Modify Address Register Instruction Type 21 23 22 21 20...

Page 413: ...es with the instruction following the NOP instruction Status Generated None affected Instruction Format No operation Instruction Type 30 see Appendix A as shown below 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISC NOP ...

Page 414: ... all unmasked interrupts to be serviced again Note Disabling interrupts does not affect serial port autobuffering or ADSP 218x DMA transfers IDMA or BDMA These operations will continue normally whether or not interrupts are enabled Status Generated None affected Instruction Format DIS INTS Instruction Type 26 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0...

Page 415: ...ts of the source are always right justified in the destination register The computation must be unconditional All ALU MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle The no...

Page 416: ...right may suggest that the data memory value is loaded into AX0 and then used in the computation all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the instruction more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually h...

Page 417: ...t if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise AS Affected only when executing the Absolute Value operation ABS Set if the source operand is negative MAC operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ MV Set if the accumulated product overflows the lower order 32 bits of the MR register Cleared otherwise SHIFT operation ASTAT 7 6 5 4 3 2 1...

Page 418: ... Shift operation with Data Memory Read Instruction Type 12 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 G 0 SF Xop Dreg I M Shift operation with Program Memory Read Instruction Type 13 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 0 SF Xop Dreg I M Z Result register Dreg Destination register SF Shifter operation AMF ALU MAC operation Y...

Page 419: ... at the end of the cycle The normal left to right order of clauses computation first register transfer second is intended to imply this In fact you may code this instruction with the order of clauses reversed The assembler produces a warning but the results are identical at the opcode level If you turn off semantics checking in the assembler s switch the warning is not issued Because of the read f...

Page 420: ...he assembler issues a warning unless semantics checking is turned off Regardless of whether or not the warning is produced however this practice is not supported The following therefore is illegal and not supported even though assembler semantics checking produces only a warning 3 AR AX0 AY0 AR MR1 Illegal Status Generated All status bits are affected in the same way as for the single function ver...

Page 421: ...ion set if the source operand is negative Cleared if the number is positive Instruction Format ALU MAC operation with Data Register Move Instruction Type 8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 Z AMF Yop Xop Dreg Dreg dest source Shift operation with Data Register Move Instruction Type 14 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 ...

Page 422: ...source are always right justified in the destination register The computation must be unconditional All ALU MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle The normal left ...

Page 423: ...on in AR is then written to memory all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the instruction more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually happens Status Generated All status bits are affected in the sa...

Page 424: ...on set if the source operand is negative Cleared if the number is positive Instruction Format ALU MAC operation with Data Memory Write Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 G 1 Z AMF Yop Xop Dreg I M ALU MAC operation with Program Memory Write Instruction Type 5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 1 Z AMF Yop Xop Dr...

Page 425: ... 13 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 1 SF Xop Dreg I M Z Result register Dreg Destination register SF Shifter operation AMF ALU MAC operation Yop Y operand Xop X operand I Indirect address register M Modify register G Data Address Generator I M registers must be from the same DAG as separated by the gray bar in the Syntax description MULTIFUNCTION COMPU...

Page 426: ... two data words No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory If two off chip accesses are required however the instruction fetch and one data fetch for example or data fetches from both program and data memory then one overhead cycle occurs In this case the program memory access occurs first then the data memory access If three off ...

Page 427: ...sses are required however the instruction fetch and one data fetch for example or data fetches from both program and data memory then one overhead cycle occurs In this case the program memory access occurs first then the data memory access If three off chip accesses are required the instruction fetch as well as data fetches from both program and data memory then two overhead cycles occur The compu...

Page 428: ...ently used in the computation all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the instruction more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually happens Status Generated All status bits are affected in the same wa...

Page 429: ...ion Format ALU MAC with Data and Program Memory Read Instruction Type 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 PD DD AMF Yop Xop PM PM DM DM I M I M PD Program Destination register DD Data Destination register AMF ALU MAC operation M Modify register Yop Y operand Xop X operand I Indirect address register MULTIFUNCTION ALU MAC with DATA PROGRAM MEMORY READ ...

Page 430: ... DM I M I M Type 2 Data Memory Write Immediate Data 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 G DATA I M Type 3 Read Write Data Memory Immediate Address 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 D RGP ADDR REG Type 4 ALU MAC with Data Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 G D Z AMF Yop Xop DREG I M ...

Page 431: ... 0 0 1 0 1 0 AMF Yop Xop 1 0 1 0 1 0 1 0 ALU codes only Type 9 Conditional ALU MAC xop yop 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND xop xop ADSP 217x ADSP 218x ADSP 21msp58 59 only 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 0 0 Xop 0 0 0 1 COND xop AND OR XOR constant ADSP 217x ADSP 218x ADSP 21msp58 59 on...

Page 432: ... 0 1 G D SF Xop DREG I M Type 13 Shift with Program Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 D SF Xop DREG I M Type 14 Shift with Internal Data Register Move 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 0 SF Xop Dest Source DREG DREG Type 15 Shift Immediate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 433: ...r saturate mode MM Alternate Multiplier placement mode GM GO Mode enable means execute internal code if possible TI Timer enable 11 Enable Mode 10 Disable Mode 0 1 no change 0 0 no change Type 19 Conditional Jump Indirect Address 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 I 0 S COND Type 20 Conditional Return 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 434: ...p 0 0 0 0 0 0 0 0 Type 25 Saturate MR 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type 26 Stack Control 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PP LP CP SPP Type 27 Call or Jump on Flag In 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Address...

Page 435: ... Operation NOP 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type 31 Idle 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type 31 Idle n Slow Idle 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 DV ...

Page 436: ...R X Y SU 0 1 0 1 0 MR X Y US 0 1 0 1 1 MR X Y UU 0 1 1 0 0 MR X Y SS 0 1 1 0 1 MR X Y SU 0 1 1 1 0 MR X Y US 0 1 1 1 1 MR X Y UU ALU Function codes 1 0 0 0 0 Y Clear when y 0 1 0 0 0 1 Y 1 PASS 1 when y 0 1 0 0 1 0 X Y C 1 0 0 1 1 X Y X when y 0 1 0 1 0 0 NOT Y 1 0 1 0 1 Y 1 0 1 1 0 X Y C 1 X C 1 when y 0 1 0 1 1 1 X Y 1 1 0 0 0 Y 1 PASS 1 when y 0 1 1 0 0 1 Y X X when y 0 1 1 0 1 0 Y X C 1 X C 1 ...

Page 437: ...an or equal GE 0 1 1 0 ALU Overflow AV 0 1 1 1 NOT ALU Overflow NOT AV 1 0 0 0 ALU Carry AC 1 0 0 1 Not ALU Carry NOT AC 1 0 1 0 X input sign negative NEG 1 0 1 1 X input sign positive POS 1 1 0 0 MAC Overflow MV 1 1 0 1 Not MAC Overflow NOT MV 1 1 1 0 Not counter expired NOT CE 1 1 1 1 Always true CP Counter Stack Pop codes 0 No change 1 Pop D Memory Access Direction codes 0 Read 1 Write DD Doubl...

Page 438: ... 1 1 0 0 MR1 1 1 0 1 MR2 1 1 1 0 SR0 1 1 1 1 SR1 DV Divisor codes for Slow Idle instruction IDLE n 0 0 0 0 Normal Idle instruction Divisor 0 0 0 0 1 Divisor 16 0 0 1 0 Divisor 32 0 1 0 0 Divisor 64 1 0 0 0 Divisor 128 FIC FI condition code 1 latched FI is 1 FLAG_IN 0 latched FI is 0 NOT FLAG_IN FO Control codes for Flag Output Pins FO FL0 FL1 FL2 0 0 No change 0 1 Toggle 1 0 Reset 1 1 Set ...

Page 439: ... codes G 0 1 0 0 I0 I4 0 1 I1 I5 1 0 I2 I6 1 1 I3 I7 LP Loop Stack Pop codes 0 No Change 1 Pop M Modify Register codes G 0 1 0 0 M0 M4 0 1 M1 M5 1 0 M2 M6 1 1 M3 M7 PD Dual Data Fetch Program Memory Destination codes 0 0 AY0 0 1 AY1 1 0 MY0 1 1 MY1 PP PC Stack Pop codes 0 No Change 1 Pop ...

Page 440: ... 0 1 0 MX0 I2 I6 SSTAT read only 0 0 1 1 MX1 I3 I7 IMASK 0 1 0 0 AY0 M0 M4 ICNTL 0 1 0 1 AY1 M1 M5 CNTR 0 1 1 0 MY0 M2 M6 SB 0 1 1 1 MY1 M3 M7 PX 1 0 0 0 SI L0 L4 RX0 1 0 0 1 SE L1 L5 TX0 1 0 1 0 AR L2 L6 RX1 1 0 1 1 MR0 L3 L7 TX1 1 1 0 0 MR1 IFC write only 1 1 0 1 MR2 OWRCNTR write only 1 1 1 0 SR0 1 1 1 1 SR1 S Jump Call codes 0 Jump 1 Call ...

Page 441: ... 1 0 1 ASHIFT HI OR 0 1 1 0 ASHIFT LO 0 1 1 1 ASHIFT LO OR 1 0 0 0 NORM HI 1 0 0 1 NORM HI OR 1 0 1 0 NORM LO 1 0 1 1 NORM LO OR 1 1 0 0 EXP HI 1 1 0 1 EXP HIX 1 1 1 0 EXP LO 1 1 1 1 Derive Block Exponent SPP Status Stack Push Pop codes 0 0 No change 0 1 No change 1 0 Push 1 1 Pop T Return Type codes 0 Return from Subroutine 1 Return from Interrupt ...

Page 442: ...0 1 1 1 ALU Overflow AV 1 0 0 0 Not ALU Carry NOT AC 1 0 0 1 ALU Carry AC 1 0 1 0 X input sign positive POS 1 0 1 1 X input sign negative NEG 1 1 0 0 Not MAC Overflow NOT MV 1 1 0 1 MAC Overflow MV 1 1 1 0 Counter expired CE 1 1 1 1 Always FOREVER X X Operand codes 0 0 0 X0 SI for shifter 0 0 1 X1 invalid for shifter 0 1 0 AR 0 1 1 MR0 1 0 0 MR1 1 0 1 MR2 1 1 0 SR0 1 1 1 SR1 Y Y Operand codes 0 0 ...

Page 443: ... bit 5 0040 01 10 01 bit 6 0080 01 11 01 bit 7 0100 10 00 01 bit 8 0200 10 01 01 bit 9 0400 10 10 01 bit 10 0800 10 11 01 bit 11 1000 11 00 01 bit 12 2000 11 01 01 bit 13 4000 11 10 01 bit 14 8000 11 11 01 bit 15 FFFE 00 00 11 bit 0 FFFD 00 01 11 bit 1 FFFB 00 10 11 bit 2 FFF7 00 11 11 bit 3 FFEF 01 00 11 bit 4 FFDF 01 01 11 bit 5 FFBF 01 10 11 bit 6 FF7F 01 11 11 bit 7 FEFF 10 00 11 bit 8 FDFF 10...

Page 444: ... conditional add subtract non restoring division algorithm As its name implies the algorithm functions by adding or subtracting the divisor to from the dividend The decision as to which operation is perform is based on the previously generated quotient bit Each add subtract operation produces a new partial remainder which will be used in the next step The phrase non restoring refers to the fact th...

Page 445: ... remainder stored in AF and AY0 If AQ is zero a subtract occurs A new value for AQ is determined by XORing the MSB of the divisor with the MSB of the dividend The 32 bit dividend is shifted left one bit and the inverted value of AQ is moved into the LSB B 1 3 Output Formats As in multiplication the format of a division result is based on the format of the input operands The division logic has been...

Page 446: ...t It can be seen that an integer integer division will produce an invalid output format of 32 16 1 0 0 1 or 17 1 To generate an integer quotient you must shift the dividend to the left one bit placing it in 31 1 format The output format for this division will be 31 16 1 1 0 1 or 16 0 You must ensure that no significant bits are lost during the left shift or an invalid result will be generated B 2 ...

Page 447: ... Unsigned Division Error Unsigned divisions can produce erroneous results if the divisor is greater than 0x7FFF You should not attempt to divide two unsigned numbers if the divisor has a one in the MSB If it is necessary to perform a such a division both operands should be shifted right one bit This will maintain the correct orientation of operands Shifting both operands may result in a one LSB er...

Page 448: ...ne otherwise the remainder is computed If it is not necessary to check for a divisor of 0x8000 this code block can be removed The code block labeled test_2 checks for a division overflow condition The absolute value of the divisor is subtracted from the absolute value of the dividend s MSW If the divisor is less then the dividend it is likely an overflow will occur If the two are equal in magnitud...

Page 449: ...1 automatically sign extends into MR2 Also the multiply must be executed with the unsigned switch To ensure that the overflow flag is clear ASTAT is set to zero before returning In both subroutines the computation of the remainder requires only one extra cycle so it is unlikely you would need to remove it for speed If it is a problem to have the multiply registers altered remove the multiply subtr...

Page 450: ... Return to calling program test_2 IF NOT AV JUMP test_3 If divisor 0x8000 then the AY0 AY1 AF ABS AY1 quotient is simply AY1 IF NOT AV JUMP recover_sign ASTAT 0x4 0x8000 divided by 0x8000 RTS so overflow test_3 AF PASS AF Check for division overflow IF NE JUMP test_4 Not equal jump test 4 AY0 0x8000 Quotient equals 1 ASTAT 0x0 Clear AS bit of ASTAT JUMP recover_sign Compute remainder test_4 AF ABS...

Page 451: ... PASS AX0 Is MSB set test_10 IF GT JUMP test_11 No so check overflow ASTAT 0x4 Yes so set overflow flag RTS Return to caller test_11 AR AY1 AX0 Is divisor dividend IF LT JUMP do_divq No so go do unsigned divide ASTAT 0x4 Set overflow flag RTS do_divq ASTAT 0 Clear AQ flag DIVQ AX0 DIVQ AX0 Do the divide DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ AX0 DIVQ ...

Page 452: ...ant words of multiple precision numbers are treated as unsigned numbers Signed numbers supported by the ADSP 2100 family are in twos complement format Signed magnitude ones complement BCD or excess n formats are not supported C 3 INTEGER OR FRACTIONAL The ADSP 2100 family supports both fractional and integer data formats with the exception that the ADSP 2100 processor does not perform integer mult...

Page 453: ... 1 0 2 2 2 2 2 2 12 11 10 1 2 3 Sign Bit Weight Bit Signed Fractional 13 3 15 14 13 2 1 0 2 2 2 2 2 2 12 11 10 1 2 3 Weight Bit Unsigned Fractional 13 3 4 3 2 2 1 0 4 3 2 2 1 0 Radix Point Radix Point In a fractional format the assumed radix point lies within the number so that some or all of the magnitude bits have a weight of less than 1 In the format shown in Figure C 2 the assumed radix point ...

Page 454: ...00 8 8 8 8 127 996093750000000 128 0 0 003906250000000 9 7 9 7 255 992187500000000 256 0 0 007812500000000 10 6 10 6 511 984375000000000 512 0 0 015625000000000 11 5 11 5 1023 968750000000000 1024 0 0 031250000000000 12 4 12 4 2047 937500000000000 2048 0 0 062500000000000 13 3 13 3 4095 875000000000000 4096 0 0 125000000000000 14 2 14 2 8191 750000000000000 8192 0 0 250000000000000 15 1 15 1 16383...

Page 455: ...tional precision For example multiplying a 1 15 number by a 5 11 number yields a 6 26 number When shifted left one bit the result is a 5 27 number or a 5 11 number plus 16 LSBs The ADSP 2100 family provides a mode called the fractional mode in which the multiplier result is always shifted left one bit before being written to the result register On the ADSP 2100 processor this mode is always active...

Page 456: ...ever A floating point number has an exponent that indicates the position of the radix point in the actual value In block floating point format a set block of data values share a common exponent To convert a block of fixed point values to block floating point format you would shift each value left by the same amount and store the shift value as the block exponent Typically block floating point form...

Page 457: ...the EXPADJ instruction which counts the number of redundant sign bits and adjusts SB is if the number of redundant sign bits is less than 2 In this example SB 1 after processing indicating that the block of data must be shifted right one bit to maintain the 2 guard bits If SB were 0 after processing the block would have to be shifted two bits right In either case the block exponent is updated to r...

Page 458: ...rupt service routines with more than four instructions however program control must be transferred to the service routine by means of a jump instruction placed at the interrupt vector location Interrupt Source Interrupt Vector Address RESET startup 0x0000 IRQ2 0x0004 highest priority SPORT0 Transmit 0x0008 SPORT0 Receive 0x000C SPORT1 Transmit or IRQ1 0x0010 SPORT1 Receive or IRQ0 0x0014 Timer 0x0...

Page 459: ... 0x0008 HIP Read to Host 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 Software Interrupt 1 0x0018 Software Interrupt 2 0x001C SPORT1 Transmit or IRQ1 0x0020 SPORT1 Receive or IRQ0 0x0024 Timer 0x0028 lowest priority Table D 4 ADSP 2171 Interrupts Interrupt Vector Addresses Interrupt Source Interrupt Vector Address RESET startup or powerup w PUCR 1 0x0000 highest priority Powerdown non maska...

Page 460: ...down non maskable 0x002C IRQ2 0x0004 HIP Write from Host 0x0008 HIP Read to Host 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 Analog DAC Transmit 0x0018 Analog ADC Receive 0x001C SPORT1 Transmit or IRQ1 0x0020 SPORT1 Receive or IRQ0 0x0024 Timer 0x0028 lowest priority Table D 6 ADSP 21msp58 59 Interrupts Interrupt Vector Addresses ...

Page 461: ...ay field These bits should always be written with zeros 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BPAGE Boot Page Select not on ADSP 2181 BWAIT Boot Wait States not on ADSP 2181 BFORCE Boot Force Bit not on ADSP 2181 PWAIT Program Memory Wait States 0 1 0 0 SPORT0 Enable 1 enabled 0 disabled set to 0 for ADSP 2105 SPORT1 Enable 1 enabled 0 disabled SPORT1 Configure 1 serial port 0 FI FO IRQ0 IRQ1 SCLK...

Page 462: ...essing only DM and PM addressing Bit reverse capability Indirect branch capability DAG1 DAG2 SPORT 0 RX0 TX0 SPORT0 Control 0x3FFA 0x3FF9 0x3FF8 0x3FF7 Multichannel enables RX 31 16 RX 15 0 TX 31 16 TX 15 0 0x3FF6 0x3FF5 0x3FF4 0x3FF3 Control SCLKDIV RFSDIV Autobuffer RX1 TX1 SPORT 1 SPORT1 Control 0x3FF2 0x3FF1 0x3FF0 0x3FEF Control SCLKDIV RFSDIV Autobuffer TIMER TPERIOD TCOUNT TSCALE 0x3FFD 0x3...

Page 463: ...9 8 7 6 5 4 3 2 1 0 DWAIT0 or DWAIT1 or DWAIT2 or DWAIT3 or DWAIT4 or 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IOWAIT0 ADSP 2181 IOWAIT1 ADSP 2181 IOWAIT2 ADSP 2181 IOWAIT3 ADSP 2181 DWAIT ADSP 2181 ROM Enable ADSP 2172 ADSP 21msp59 1 enable 0 disable Waitstate Control Register DM 0x3FFE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPERIOD Period Register TCOUNT Counter Register TSCALE Scaling Register 0 0 0 0 0 ...

Page 464: ...ro fill unused MSBs 01 right justify sign extend into unused MSBs 10 compand using µ law 11 compand using A law ITFS Internal Transmit Frame Sync Enable or MCL Multichannel Length 1 32 words 0 24 words Only If Multichannel Mode Enabled 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Only If Multichannel Mode Enabled Only If Multichannel Mode Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 465: ...ble 0 0 0 0 RBUF Receive Autobuffering Enable TIREG TMREG RIREG RMREG 0 0 BIASRND MAC Biased Rounding Control Bit ADSP 2171 ADSP 2181 ADSP 21msp58 59 only CLKODIS CLKOUT Disable Control Bit ADSP 2171 ADSP 2181 ADSP 21msp58 59 only Memory Mapped Registers SPORT0 SCLKDIV Serial Clock Divide Modulus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPORT0 RFSDIV Receive Fram...

Page 466: ... Receive Frame Sync SLEN Serial Word Length 1 DTYPE Data Format 00 right justify zero fill unused MSBs 01 right justify sign extend into unused MSBs 10 compand using µ law 11 compand using A law ITFS Internal Transmit Frame Sync Enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM 0x3FF2 SPORT1 Control Register SPORT1 SCLKDIV Serial Clock Divide Modulus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9...

Page 467: ...RCE and PUCR are only on the ADSP 2171 ADSP 2181 and ADSP 21msp58 59 processors DM 0x3FEF Not on ADSP 21msp5x Default bit values at reset are shown if no value is shown the bit is undefined at reset Reserved bits are shown on a gray field these bits should always be written with zeros Memory Mapped Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATBUF DAC Transmit Autobuffer Enable ARBUF ADC Recei...

Page 468: ...t Multiplexer Select 1 AUX input 0 NORM input OG0 OG1 OG2 OG2 OG1 OG0 DAC Output Gain DAC PGA 0 0 0 0 0 0 0 0 0 IG0 ADC Input Gain ADC PGA Gain 6 dB 3 dB 0 dB 3 dB 6 dB 9 dB 12 dB 15 dB OG2 0 0 0 0 1 1 1 1 OG1 0 0 1 1 0 0 1 1 OG0 0 1 0 1 0 1 0 1 OG2 OG1 OG0 DAC Output Gain DAC PGA Gain 0 dB 6 dB 20 dB 26 dB IG1 0 0 1 1 IG0 0 1 0 1 IG1 IG0 ADC Input Gain ADC PGA ADC Offset ADSP 21msp5x only DM 0x3F...

Page 469: ...R0 Write Host HDR1 Write Host HDR2 Write Host HDR3 Write Host HDR4 Write Host HDR5 Write Host HDR0 Read Host HDR1 Read Host HDR2 Read Host HDR3 Read Host HDR4 Read Host HDR5 Read DM 0x3FE8 ADSP 2171 ADSP 2111 ADSP 21msp5x only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OVERWRITE MODE SOFTWARE RESET 21xx HDR0 Write 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 21xx HDR1 Write 21xx HDR2 Write 21xx HDR3 Write 21xx HDR4...

Page 470: ...rite Host HDR2 Write Host HDR3 Write Host HDR4 Write Host HDR5 Write ADSP 2171 ADSP 2111 ADSP 21msp5x only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDR5 HIP Data Registers DM 0x3FE5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDR4 DM 0x3FE4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDR3 DM 0x3FE3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDR2 DM 0x3FE2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDR1 DM 0x3FE1 15 14 13 ...

Page 471: ...ts should always be written with zeros Memory Mapped Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMWAIT 1 0 1 1 1 1 0 PFTYPE 1 Output 0 Input 1 0 0 0 0 CMSSEL 0 0 0 0 DM BM IOM PM 1 Enable CMS 0 Disable CMS Programmable Flag Composite Select Control ADSP 2181 only DM 0x3FE6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PFDATA Programmable Flag Data ADSP 2181 only DM 0x3FE5 ...

Page 472: ... halt during BDMA context reset when done BTYPE see table BTYPE 00 01 10 11 Internal Memory Space PM DM DM DM Word Size 24 16 8 8 Alignment full full MSB LSB word word BDMA Word Count MMAP 0 and BMODE 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWCOUNT 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWCOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 or BDMA Word Count MMAP 1 or BMODE 1 ADSP...

Page 473: ...s BDMA External Address ADSP 2181 only DM 0x3FE2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEAD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIAD BDMA Internal Address ADSP 2181 only DM 0x3FE1 Memory Mapped Registers IDMA Control ADSP 2181 only DM 0x3FE0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDMAA Starting address IDMAD Destination memory type 0...

Page 474: ...2 1 0 Interrupt Nesting 1 edge 0 level 1 enable 0 disable IRQ0 Sensitivity IRQ1 Sensitivity IRQ2 Sensitivity MSTAT ICNTL ASTAT PC Stack Empty PC Stack Overflow Count Stack Empty Count Stack Overflow Status Stack Empty Status Stack Overflow Loop Stack Empty Loop Stack Overflow 0 1 2 3 4 5 6 7 1 0 1 0 1 0 1 0 ALU Result Zero ALU Result Negative ALU Overflow ALU Carry ALU X Input Sign ALU Quotient MA...

Page 475: ...IRQ2 INTERRUPT FORCE BITS INTERRUPT CLEAR BITS 0 0 0 0 0 0 0 0 0 0 0 0 SPORT0 Receive SPORT0 Transmit IRQ2 SPORT0 Receive must be set to 0 for ADSP 2105 SPORT0 Transmit must be set to 0 for ADSP 2105 must be set to 0 for ADSP 2105 must be set to 0 for ADSP 2105 IFC write only IMASK 5 4 3 2 1 0 Timer SPORT0 Receive must be set to 0 for ADSP 2105 0 0 0 0 0 0 SPORT0 Transmit must be set to 0 for ADSP...

Page 476: ... 16 Non Memory Mapped Registers 5 4 3 2 1 0 0 0 0 0 0 0 7 6 0 0 INTERRUPT ENABLES Timer SPORT0 Receive SPORT0 Transmit SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 HIP Read HIP Write IRQ2 1 enable 0 disable mask IMASK ADSP 2111 ...

Page 477: ... 0 0 0 0 IRQ2 15 14 13 12 0 0 0 0 Timer SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 IRQ2 BDMA Interrupt INTERRUPT FORCE BITS INTERRUPT CLEAR BITS SPORT0 Receive SPORT0 Transmit SPORT0 Receive SPORT0 Transmit IRQE BDMA Interrupt IRQE 5 4 3 2 1 0 0 0 0 0 0 0 7 6 0 0 SPORT0 Receive IRQL0 IRQL1 SPORT0 Transmit 9 8 0 0 BDMA Interrupt IRQE Timer SPORT1 R...

Page 478: ... or IRQ1 IRQ2 INTERRUPT ENABLES 1 enable 0 disable mask 11 10 9 8 7 6 5 4 3 2 1 0 Timer 0 0 0 0 0 0 0 0 0 0 0 0 IRQ2 15 14 13 12 0 0 0 0 Timer SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Software Interrupt 0 Software Interrupt 1 SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 IRQ2 Software Interrupt 0 Software Interrupt 1 INTERRUPT FORCE BITS INTERRUPT CLEAR BITS SPORT0 Receive SPORT0 Transmit S...

Page 479: ...nsmit 9 8 0 0 ADC Receive DAC Transmit Timer SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 IRQ2 INTERRUPT ENABLES 1 enable 0 disable mask ADSP 21msp5x 11 10 9 8 7 6 5 4 3 2 1 0 Timer 0 0 0 0 0 0 0 0 0 0 0 0 IRQ2 15 14 13 12 0 0 0 0 Timer SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 ADC Receive DAC Transmit SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 IRQ2 ADC Receive DAC Transmit INTERRUPT FO...

Page 480: ...essing only DM and PM addressing Bit reverse capability Indirect branch capability DAG1 DAG2 SPORT 0 RX0 TX0 SPORT0 Control 0x3FFA 0x3FF9 0x3FF8 0x3FF7 Multichannel enables RX 31 16 RX 15 0 TX 31 16 TX 15 0 0x3FF6 0x3FF5 0x3FF4 0x3FF3 Control SCLKDIV RFSDIV Autobuffer RX1 TX1 SPORT 1 SPORT1 Control 0x3FF2 0x3FF1 0x3FF0 0x3FEF Control SCLKDIV RFSDIV Autobuffer TIMER TPERIOD TCOUNT TSCALE 0x3FFD 0x3...

Page 481: ...ithmetic shift 2 3 2 22 2 28 AS sign 2 5 2 13 ASHIFT 2 31 Assembler 1 10 Assembler directives 12 10 14 1 Index X 1 ASTAT 2 10 2 13 2 19 2 24 2 26 2 36 3 21 3 24 12 5 Autobuffer service 5 39 Autobuffer timing 5 37 Autobuffering 5 3 5 4 5 26 5 32 5 38 5 40 5 41 8 1 8 9 8 10 8 11 8 12 8 13 8 14 8 15 9 5 9 23 15 18 Autobuffer control register 5 27 AV overflow 2 2 2 5 2 8 2 9 2 13 2 26 2 36 AX0 registe...

Page 482: ... of loop 3 7 3 10 EPROM 1 4 10 17 Branching 3 1 BTYPE 11 9 Buffer length 4 5 Bus exchange 1 5 1 8 2 15 4 1 4 9 12 6 Bus grant BG 3 18 9 15 Bus request BR 5 38 10 15 10 21 13 2 Buses 1 3 1 8 BWAIT 10 17 BWCOUNT 9 13 11 7 Byte memory 11 9 C C Compiler 1 10 C language 14 3 CALL 3 4 3 8 3 9 3 24 Carry AC 2 2 2 5 2 8 2 13 2 36 Carry in CI 2 5 Chip enable 10 3 Circular buffer addressing 1 5 1 7 4 1 4 3 ...

Page 483: ...IP write interrupt 7 4 HMASK register 3 15 7 4 7 10 7 11 12 8 HMD0 7 3 7 4 HMD1 7 4 Hold offs 11 25 Host 1 2 Host data bus 7 4 Host handshaking 7 7 Host interface port HIP 1 2 1 9 3 15 7 1 7 4 9 4 10 15 12 2 13 13 Host interface timing 7 11 Host read strobe 7 4 Host write strobe 7 4 HSEL 7 3 HSIZE 7 3 7 11 HSR registers 7 4 7 5 9 25 I I registers 4 2 4 3 5 26 5 28 8 14 12 2 IACK 11 12 11 13 11 25 ...

Page 484: ... 10 6 10 15 Mode bits 12 5 Mode control 12 5 15 16 Mode status register MSTAT 3 12 3 22 Modify M registers 4 1 4 2 4 3 5 26 5 28 Modulo addressing 4 1 4 4 Modulus logic 4 3 MOVE instructions 15 13 MR register 2 13 2 15 2 16 2 18 2 20 2 22 MR0 register 2 13 2 15 2 18 MR1 register 2 13 2 15 2 19 2 20 MR2 register 2 13 2 15 2 19 2 20 MSTAT 1 7 2 8 2 9 2 16 2 24 3 12 3 14 3 20 3 22 4 2 6 1 12 5 Multic...

Page 485: ... 3 15 6 Program memory write 10 3 Program sequencer 3 1 3 5 12 2 12 4 Programming model 12 1 PUCR 9 18 PWAIT 10 5 PWD pin 9 19 PWDACK pin 9 29 PX registers 1 5 4 9 4 10 Q Quotient format 2 12 R R bus 1 6 2 15 2 18 2 22 RAM 10 6 Read operation 15 12 Receive companding latency 5 40 Receive frame sync 5 11 5 12 5 30 Receive interrupt SPORT 5 4 5 36 Receive register 5 6 Receive word enables 5 31 Recei...

Page 486: ...s condition 3 6 3 25 Status logic 3 4 Status registers 3 15 3 20 Status stack 3 16 3 20 3 22 12 5 Stolen cycles 15 18 Subroutine 3 9 Subtract with borrow 2 8 Synchronization delay 9 3 Synchronization serial clk to processor clk 5 38 System Builder 1 10 System Control Register 9 14 9 15 10 17 15 12 E 1 System interface 9 1 T T1 interface 5 31 TCOUNT 6 1 6 2 6 3 6 4 12 6 TDV 5 32 Termination conditi...

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