11
DMA Ports
11 – 13
Four IDMA port inputs control when the port is selected (
IS
) for read
(
IRD
), write (
IWR
), or address latch (IAL) operations on its address/data
bus (IAD0-15). The IDMA Port Select (
IS
) line acts as a chip select for all
IDMA operations.
Asserting the IDMA Port Select (
IS
) and address latch enable (IAL) directs
the ADSP-2181 to write the address on the IAD0-15 bus into the IDMA
Control Register. This register, shown in Figure 11.7, is memory-mapped
at address DM(0x3FE0). Note that the latched address (IDMAA) cannot be
read back by the host.
Asserting the IDMA Port Select (
IS
) and Read strobe (
IRD
) inputs directs the
ADSP-2181 to output the contents of the memory location pointed to by the
IDMA Control register onto the IDMA data bus.
Asserting the IDMA Port Select (
IS
) and Write strobe (
IWR
) inputs directs the
ADSP-2181 to write the input from the IDMA data bus to the address pointed
to by the IDMA register.
When reading/writing to Data Memory, the IDMA data bus pins make up a
16-bit Data Memory word. When reading/writing to Program Memory, the
upper 16 bits of the 24-bit Program Memory word are sent first on the IDMA
data bus pins. On the next IDMA Port read/write, the lowest 8 bits of the
Program Memory word are sent on bits 0-7 of the IDMA data bus. For reads,
the ADSP-2181 sets data bus lines 8-15 to 0; for writes, the ADSP-2181 ignores
bits 8-15 from the host.
The IDMA Port Access Acknowledge (
IACK
) line identifies completion of
data reads/write operations. It also acts as a busy signal for the IDMA Port.
External devices must wait for this signal to go low before modifying IDMA
Control register or starting the next read/write operation.
Figure 11.7 IDMA Control Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDMA Control Register
DM(0x3FE0)
IDMAA
Starting address
IDMAD
Destination memory type:
0=PM
1=DM
