11 DMA Ports
11 – 16
• Host writes to internal Program Memory take two IDMA writes (for a
24-bit word through a 16-bit port). If an IDMA address latch cycle or a
ADSP-2181 write to the IDMA Control Register occurs after a first
Program Memory write cycle, the IDMA port “loses” the Program
Memory word without changing the contents of memory. The next
IDMA read or write accesses the address selected by the new contents
of the IDMA Control Register.
• Host memory accesses through the IDMA port that occur while the
ADSP-2181 is in powerdown have some restrictions. For information on
powerdown restrictions on IDMA port transfers, see the System Interface
chapter of this manual.
11.3.3
Modifying Control Registers for IDMA
The ADSP-2181’s memory-mapped control registers are protected from
DMA transfers to prevent accidental corruption. You may want the host
processor to read and write these registers, however, in order to
determine the ADSP-2181’s configuration and then change it.
To read the memory-mapped control registers, you must first transfer the
contents of these locations to another area of internal RAM. The following
code segment shows a loop that performs this task:
.const NUM_REG=32;
.var/dm/ram temp_array[NUM_REG];
i0=^temp_array;
l0=0;
i1=0x3fe0;
l1=0;
m1=1;
cntr=NUM_REG;
do transfer until ce;
ax0=dm(i1,m1);
transfer:
dm(i0,m1)=ax0;
To have the host write to the memory-mapped control registers, you must
first load the values to a temporary buffer (through the IDMA port) and
then signal the ADSP-2181 to transfer the contents of the temporary buffer
to the memory-mapped control registers. This transfer is performed in a
similar manner as the code shown above. You should set up some form of
signalling between the host and the ADSP-2181, either interrupts, flag
I/O, or a mailbox register. This will provide a mechanism for the host to
tell the DSP when to perform an operation and vice versa.
