12
Programming Model
12 – 1
12.1
OVERVIEW
From a programming standpoint, the ADSP-21xx processors consist of
three computational units, two data address generators, and a program
sequencer, plus on-chip peripherals and memory that vary with each
processor. Almost all operations using these architectural components
involve one or more registers—to store data, to keep track of values such
as pointers, or to specify operating modes, for example.
Internal registers hold data, addresses, control information or status
information. For example, AX0 stores an ALU operand (data); I4 stores a
DAG2 pointer (address); ASTAT contains status flags from arithmetic
operations; and fields in the Wait State register control the number of wait
states for different zones of external memory.
There are two types of accesses for registers. Dedicated registers such as
MX0 and IMASK can be read and written explicitly in assembly language.
For example:
MX0=1234;
IMASK=0xF;
Memory-mapped registers—the System Control Register, Wait State
Control Register, timer registers, SPORT registers, etc.—are accessed by
reading and writing the corresponding data memory locations. For
example, this code clears the Wait State Control Register, which is mapped
to data memory location 0x3FFE:
AX0=0;
DM(0x3FFE)=AX0;
(AX0 is used to hold the constant 0 because there is no instruction to write
an immediate data value to memory using an immediate address.)
