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AC101
Preliminary Data Sheet
06/04/01
B r o a d c o m
Page 8
Media Interface
Document AC101-DS01-405-R¥¥¥¥¥
put states. If a multi-function pin is pulled up during reset to select a particular function, then that LED output would become
active low, and the LED circuit must be designed accordingly, and vice versa.
In addition to the individual LED configurations, an advanced LED circuit has been implemented, as illustrated in ”Advanced
LED Selections” on page 19.
A
UTO
-N
EGOTIATION
By definition the 10/100 Transceiver is able to run at either 10 Mbps over Twisted Pair Copper (10BASE-T), 100 Mpbs over
Twisted Pair Copper (100BASE-TX) or 100 Mpbs over Fiber Optics (100BASE-FX). In addition the PHY is able to run in
either half-duplex (repeater mode) or full-duplex. To determine the operational state, the PHY has hardware selects and soft-
ware selects while also supporting Auto- Negotiation and Parallel Detection. To run in 100BASE-FX mode, the selection
must be done through hardware configuration. There is no support for Auto-Negotiation of the FX interface.
Not all of the above combinations are possible due to limitations of the environment and the 802.3 standards. Legitimate
operating states are:
•
10BASE-T Half-duplex
•
10BASE-T Full-duplex
•
100BASE-TX Half-duplex
•
100BASE-TX Full-duplex
•
100BASE-FX Half-duplex
•
100BASE-FX Full-duplex
The PHY can be hardware configured to force any one of the above mentioned modes (see ”Control and Status Pins” on
page 14). By forcing the mode, the PHY will only run in that mode, hence limiting the locations where the product will operate.
The PHY is able to negotiate its mode of operation in the twisted pair environment using the Auto-Negotiation mechanism
defined in the clause 28 of IEEE 802.3u specification. ANeg can be enabled or disabled by hardware (ANEGA pin) or soft-
ware (Reg. 0.12) control. When the ANeg is enabled, the PHY chooses its mode of operation by advertising its abilities and
comparing them with the ability received from its link partner. It can be configured to advertise 100BASE-TX or 10BASE-T
operating in either full or half-duplex.
Register 4 (see ”Register 4: Auto-Negotiation Advertisement Register” on page 26) contains the current capabilities, speed
and duplex, of the PHY, determined through hardware selects (TECH[2:0], see ”Control and Status Pins” on page 14) or
chip defaults. The contents of Reg. 4 is sent to its link partner during the ANeg process using Fast Link Pulses (FLPs). An
FLP is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a Link Code Word. After
reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. Therefore, the hardware has
priority over software.
When ANeg is enabled, the PHY sends out FLPs during the following conditions:
•
Power on
•
Link loss
•
Restart command
During this period, the PHY continually sends out FLPs while monitoring the incoming FLPs from the link partner to deter-
mine their optimal mode of operation. If FLPs are not detected during this phase of operation, Parallel Detection mode is
entered (see ”Parallel Detection” on page 9).
When the PHY receives 3 identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words
in Reg. 5 (see ”Register 5: Auto-Negotiation Link Partner Ability Register” on page 27), sets the acknowledge bit it the gen-
erated FLPs, and waits to receive 3 identical code word with the acknowledge bit set from the link partner. Once this occurs
the PHY configures itself to the highest technology that is common to both ends.