Preliminary Data Sheet
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AC101
06/04/01
B r o a d c o m
Document AC101-DS01-405-R¥¥¥¥¥
Media Interface
Page 7
Adaptive Equalizer
The PHY is designed to accommodate a maximum of 150 meters UTP CAT-5 cable. An AT&T 1061 CAT-5 cable of this
length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst case
cable attenuation is around 24-26 dB as defined by TP-PMD specification.
The amplitude and phase distortion from the cable cause inter-symbol interference (ISI) which makes clock and data recov-
ery difficult. The adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable. The
equalizer has the ability to changes its equalizer frequency response according to the cable length. The equalizer will tune
itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable.
PLL Clock Synthesizer
The PHY includes an on-chip PLL clock synthesizer that generate 25 MHz and 125 MHz clocks for the 100BASE-TX circuit-
ry. It also generates 20 MHz and 100 MHz clocks for the 10BaseT and ANeg circuitry. The PLL clock generator uses a fully
differential VCO cell that introduces very low jitter. The Zero Dead Zone Phase Detection method implemented in the PHY
design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further re-
duce jitter at different loop filter voltages. The on-chip loop filter eliminates the need for external components and minimizes
the external noise sensitivity. Only one external 25 MHz crystal or clock source is required as a reference clock.
After power-on or reset, the PLL clock synthesizer generates the 20 MHz clock output until the 100BASE-X operation mode
is selected.
Jabber and SQE (Heartbeat)
After the MAC transmitter exceeds the jabber timer (46mS), the transmit and loopback functions will be disabled and COL
signal get asserted. After TX_EN goes low for more than 500 ms, the TP transmitter will reactivate and COL gets de-assert-
ed. Setting Jabber Disable will disable the jabber function.
When the SQE test is enabled, a COL pulse with 5-15BT is asserted after each transmitted packet. SQE is enabled in
10BASE-T by default, and can be disabled via SQE Test Inhibit.
Reverse Polarity Detection and Correction
Certain cable plants have crossed wiring on the twisted pairs; the reversal of TXIN and TXIP. Under normal circumstances
this would cause the receive circuitry to reject all data. When the Auto Polarity Disable bit (see ”Register 16: Polarity and
Interrupt Level Register” on page 29) is cleared, the PHY has the ability to detect the fact that either 8 NLPs or a burst of
FLPs are inverted and automatically reverse the receiver’s polarity. The polarity state is stored in the Reverse Polarity bit.
If the Auto Polarity Disable bit is set, then the Reverse Polarity bit (see ”Register 16: Polarity and Interrupt Level Register”
on page 29) can be written to force the polarity reversal of the receiver.Initialization and Setup
H
ARDWARE
C
ONFIGURATION
Several different states of operation can be chosen through hardware configuration. External pins may be pulled either high
or low at reset time (see ”Control and Status Pins” on page 14). The combination of high and low values determines the
power on state of the device.
Many of these pins are multi-function pins which change their meaning when reset ends.
S
OFTWARE
C
ONFIGURATION
Several different states of operation can be chosen through software configuration. Please refer to ”Serial Management In-
terface (SMI)” on page 1 and Section 4 ”Register Descriptions” on page 23.
LED Outputs
Individual LED outputs are available to indicate Speed, Duplex, Collision, Receive, Transmit, and Link. These multi-function
pins are inputs during reset and LED output pins thereafter. The level of these pins during reset determines their active out-