Altima AC101 Series, Manual, Page: 24 / 64

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AC101 Preliminary Data Sheet
06/04/01
B r o a d c o m
Page 14 Pin Descriptions Document AC101-DS01-405-R¥¥¥¥¥
S
PECIAL
/T
EST
P
INS
C
ONTROL AND
S
TATUS
P
INS
Table 6: Special/Test Pins
Pin Name 101TF 101QF Type Description
CLK25 6 11 O CLK25 provides a continuous 25 MHz clock if CLK25EN is asserted dur-
ing reset.
Reserved 7 12 I, D
TEST0
TEST1
TEST2
TEST3
66
67
68
62
86
87
88
82
AO/AI
AO/AI
AO
AO/AI
TEST [3:0] pins are used as the test-mode output monitor pin. Internal
pull-down in normal 100BASE-TX or 10BASE-T mode.
RST* 8 13 I, U Reset. An active low input will force a known initialization state. The re-
set pulse duration must be > 150 us. Setting MII Reg. 0.15 (see ”Register
0: Control Register” on page 24) will assert software reset, which has the
same functionality as the hardware reset.
PWRDN 9 14 I, D Power Down. Driving this pin high will power down the device’s analog
modules and reset the device’s digital circuits. The device still responds
to the management MDC/MDIO data. Power-down mode can also be
achieved by setting MII Reg. 0.11 (see ”Register 0: Control Register” on
page 24).
RIBB 72 92 A Reference Bias Resistor. To be tied to analog ground through an exter-
nal 10.0 K (1%) resistor.
CKIN 5 10 I, D Clock Input. Connects to a 25 MHz clock source. When a crystal input is
used, this pin should be tied low to ground via 1K
Ω
.
XTLN
XTLP
74
75
94
95
AI Crystal inputs. To be connected to a 25 MHz crystal. CKIN should be tied
low when the crystal is used as a clock source.
Table 7: Control and Status Pins
Pin Name 101TF 101QF Type Description
ISODEF 2 7 I, D Isolate Default. If pulled high during reset, the MII interface will be tri-
stated for use with multiple PHYs in a single MAC. The status of this pin
will be latched in to Register 0.10 (see ”Register 0: Control Register” on
page 24).
ISO 3 8 I, D Isolate. The MII output pins assume high impedance state when ISO is
asserted high. However, the MII input pins still respond to data. This al-
lows multiple PHYs to be attached to the same MII interface. The same
isolate condition can also be achieved by setting MII Reg. 0.10 (see
”Register 0: Control Register” on page 24). In repeater mode, ISO will
not tri-state CRS pin (see ”MII (Media Independent Interface) 100 PCS
Bypass Pins” on page 12).