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AC101
Preliminary Data Sheet
06/04/01
B r o a d c o m
Page 12
Pin Descriptions
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MII (M
EDIA
I
NDEPENDENT
I
NTERFACE
) 100 PCS B
YPASS
P
INS
Outputs tri-state during MII isolation.
FXRN
FXRP
66
67
86
87
AO/AI
AO/AI
Receive input positive and negative for 100BASE-FX when FX_DIS
pin is pulled low.
FXTP
FXTN
69
70
89
90
AO
AO
Transmit output positive and negative for 100BASE-FX when FX_DIS
pin is pulled low.
SDP
62
82
AO/AI
Signal Detect input from Fiber-optic transceiver when FX_DIS pin is
pulled low
Table 3:
MII (Media Independent Interface) 100 PCS Bypass Pins
Pin Name
101TF
101QF
Type
Description
MDIO
21
31
I/O, U
Management Data Input/Output. Bi-directional data interface. A 1.5K pull
up resistor is required (as specified in IEEE-802.3).
MDC
22
32
I
Management Data Clock. 0 to 25 MHz clock sourced by the MAC for
transfer of MDIO data.
RXD [3]
RXD [2]
RXD [1]
RXD [0]
23
24
25
26
33
34
35
36
O, Z
MII received data. The data is synchronous with RX_CLK when RX_DV
is active.
PCS Bypass RXD[3:0]
RX_DV
29
39
O, Z
Receive Data Valid. Asserted high when valid data is present on the
RX[3:0]. In 100Base mode, it is asserted with the first nibble of preamble
and is de-asserted when the last data nibble has been received. In
10Base mode, it is asserted when the SFD (Start-of-Frame) delimiter is
detected and de-asserted at end of data.
RX_CLK
30
40
O, Z
Receive Clock. A continuous clock which provides timing reference for
RX_DV, RX_ER and RXD[3:0] signals. 25 MHz in 100Base and 2.5 MHz
in 10Base. To reduce system power consumption RX_CLK is held inac-
tive (low) when no data is received and Reg. 16.0 is enabled.
RX_ER
RXD[4]
31
41
O, Z
MII Receive Error. Active high to indicate an error has been detected dur-
ing frame reception during 100Base mode.
PCS Bypass RXD[4]
TX_ER
TXD[4]
32
42
I
MII Transmit Error. When TX_ER is asserted, it will cause the 4B/5B en-
coding process to substitute the transmit error code-group /H/ for the en-
coded data word during 100Base mode.
PCS Bypass TXD[4]
TX_CLK
33
43
O, Z
Transmit Clock. A continuous clock which provides timing reference for
TX_EN, TX_ER and TXD[3:0] signals. It is 25 MHz in 100Base and 2.5
MHz in 10Base.
TX_EN
34
44
I
Transmit Enable. TX_EN is asserted by the MAC to indicate that valid
data is present on TXD[3:0].
Table 2:
MDI (Media Dependent) Pins (Cont.)
Pin Name
101TF
101QF
Type
Description