Preliminary Data Sheet
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AC101
06/04/01
B r o a d c o m
Document AC101-DS01-405-R¥¥¥¥¥
Media Interface
Page 5
Baseline Wander Compensation
The 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC components of the incoming sig-
nal, thus the DC offset of the differential receive inputs can drift. The shifting of the signal level, coupled with non-zero rise
and fall times of the serial stream can cause pulse-width distortion. This creates jitter and possible increase in the bit error
rates. Therefore, a DC restoration circuit is needed to compensate for the attenuation of the DC component. This PHY im-
plements a patent-pending DC restoration circuit. Unlike the traditional implementation, the circuit does not need the feed-
back information from the slicer or the clock recovery circuit. This design simplifies the circuit design and eliminates any
random/systematic offset on the receive path. In the 10BaseT and the 100BASE-FX modes, the baseline wander correction
circuit is not required, and therefore is disabled.
Clock/Data Recovery
The equalized MLT-3 signal passes through the slicer circuit, and gets converted to NRZI format. The PHY uses a propri-
etary mixed-signal phase locked loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock
is used to re-time the data stream and set the data boundaries. The transmit clock is locked to the 25 MHz clock input while
the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream,
extracts the 125 MHz clock, and uses it for the bit framing for the recovered data. The recovered 125 MHz clock is also used
to generate the 25 MHz RX_CLK signal. The PLL requires no external components for its operation and has high noise im-
munity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time after
power-on is less than 60 transitions. The PLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal
transitions. When no valid data is present, i.e. when the SD is de-asserted, the PLL will switch and lock on to TX_CLK. This
provides a continuously running RX_CLK. At the PCS interface, the 5 bit data RXD[4:0] is synchronized to the 25 MHz
RX_CLK. See ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12.
Decoder/De-scrambler
The de-scrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence repre-
senting consecutive idle codes. The de-scrambler acquires lock on the data stream by recognizing IDLE bursts of 30 or more
bits and locks its frequency to its de-ciphering LFSR.
Once lock is acquired, the device can operate with an inter-packet-gap (IPG) as low as 40 nS. However, before lock is ac-
quired, the de-scrambler needs a minimum of 270 nS of consecutive idles in between packets in order to acquire lock.
The de-ciphering logic also tracks the number of consecutive errors received while the RX_DV (see ”MII (Media Independent
Interface) 100 PCS Bypass Pins” on page 12) is asserted. Once the error counter exceeds its limit currently set to 64 con-
secutive errors, the logic assumes that the lock has been lost, and the de-cipher circuit resets itself. The process of regaining
lock will start again.
Stream cipher de-scrambler is not used in the 100BASE-FX and the 10BASE-T modes.
Link Monitor
Signal level is detected through a squelch detection circuitry. A signal detect (SD) circuit allows the equalizer to assert high
whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mV. This is ap-
proximately 40% of a normal signal voltage level. In addition, the energy level must be sustained for longer than 2~3
µ
S in
order for the signal detect signal to stay on. The SD gets de-asserted approximately 1~2
µ
s after the energy level drops
consistently below 300 mV from peak to ground.
The link signal is forced low during a local loopback operation (Loopback register bit is set) and forced to high when a remote
loopback is taking place (EN_RPBK is set, see ”Register 21: Mode Control Register” on page 32).
In forced 100BASE-TX mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor
enters in the “link fail” state and NLP's are transmitted. When a valid signal is detected for a minimum period of time, the link
monitor enters Link Pass State and transmits MLT-3 signal.