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Preliminary Data Sheet

■

 AC101

06/04/01

        

   

B r o a d c o m

Document  AC101-DS01-405-R¥¥¥¥¥

Pin Descriptions

Page  15 

TECH [2]

/DUPLEX

TECH[1]

/SPDSEL

TECH[0]

/LINK_BT

53

54

55

68

69

70

I, U

I, U

I, U

Technology Select.

• When ANEGA pin is set to high, TECH[2:0] will then set the negotia-

ble capabilities. (See ”Technology Selections” on page 18.) 

• When ANEGA is set to low, TECH[2:0] will then set the forced capa-

bilities. (See ”Technology Selections” on page 18.) 

When the PHY is in PCS bypass mode (PCSBP pin pull high), 
TECH[2:0] are as follows:

• TECH[0] is 10BaseT Link input (High Active). The MAC is responsible 

for ANeg, and creates 10BaseT Link signal.

• TECH[1] is SPDSEL for the SYMBOL interface. When it is de-assert-

ed, only the 10BaseT driver is used to transmit 10BASE-T signals, 
NLP and FLP.

• TECH[2] is DUPLEX. The MAC is responsible for indicating the du-

plex operation mode. The input values of TECH[2] and TECH[0] in 
this mode are used for LED display only.

ANEGA

56

71

I, U

Auto-Negotiation Ability. ANeg is enabled when this pin is pulled high. 
When this pin is pulled low, mode of operation is depended on 
TECH[2:0]. This pin also controls the ANEGA bit in MII Reg.1.3.

ACTIVITY

56

71

I, U

Activity. In PCS bypass mode (PCSBP pin pull high), the MAC provides 
the activity signal to generate the activity LED signal.

RPTR

61

81

I

Repeater Mode. When this pin is asserted high via 1 K 

Ω

, repeater mode 

will be enabled. In repeater mode, CRS becomes receive activity. SQE 
test function is disabled in 10BASE-T mode. Repeater mode can also 
enabled via MII Reg. 16.15. Requires a pull down of 1 K 

Ω

 resistor when 

used in NIC applications.

PCSBP

1

6

I, D

PCS Bypass. 100BASE-TX or 10BASE-T enter PCS bypass if PCSBP 
is asserted high at reset.

GPIO[0]

7W*

19

24

I/O, U

General Purpose I/O. These pins can be configured as either an input or 
output by the management Reg. 16.[6].

7W - If the GPIO[0] is pull low by 1 K

Ω

 during reset, the 10BASE-T 7-

wire interface is enabled.

GPIO[1]

TP125

20

25

I/O, D

General Purpose I/O. These pins can be configured as either an input or 
output by the management Reg. 16.[8]. In MII mode, GPIO[1] is used to 
select the 10BASE-T operation mode. With internal pull down, the de-
vice defaults to standard MII interface for 10BASE-T after reset.

TP125 - If the GPIO[1] pin is pulled high by a 1 K

Ω

 resistor during Reset, 

the 1.25:1 transformer ratio transmitter is enabled. A 1:1 type transform-
er is selected by default.

Table 7:

Control and Status Pins  (Cont.)

Pin Name

101TF

101QF

Type

Description

Summary of Contents for AC101 Series

Page 1: ...T signal MAC interfaces to support 10 100 MII 100M only Symbol Mode 10M only Symbol Mode and 10M only 7 wire interface are included The AC101TF and the AC101QF are the same product in differ ent pack...

Page 2: ...ion the Broadcom component s identified herein is not designed intended or certified for use in any military nuclear medical mass transportation aviation navigations pollution control hazardous substa...

Page 3: ...pass 3 10 Mbps PCS Bypass 3 Media Interface 3 10BASE T Interface 3 Transmit Function 3 Receive Function 3 Link Monitor 3 100BASE TX Interface 3 Transmit Function 4 Parallel to Serial NRZ to NRZI and M...

Page 4: ...Input 10 Section 2 Signal Definitions and Pin Assignments 11 Pin Descriptions 11 PHY Address Pins 11 MDI Media Dependent Interface Pins 11 MII Media Independent Interface 100 PCS Bypass Pins 12 10 Mbp...

Page 5: ...er 30 Register 19 Power Loopback Register 31 Register 20 Cable Measurement Register 31 Register 21 Mode Control Register 32 Register 24 Receive Error Counter Register 33 4B 5B Code Group Table 33 SMI...

Page 6: ...t System Timing 45 10BASE T 7 Wire Receive System Timing 46 10BASE T 7 Wire Collision Timing 46 Recommended Board Circuitry 47 TX Application Termination 47 FX Application Termination 48 Power and Gro...

Page 7: ...SE TX FX MII Transmit Timing 41 Figure 9 100BASE TX FX MII Receive Timing 42 Figure 10 10BASE T MII Transmit Timing 43 Figure 11 10BASE T MII Receive Timing 44 Figure 12 10BASE T 7 WireTransmit Timing...

Page 8: ...AC101 Preliminary Data Sheet LIST OF FIGURES 06 04 01 Broadcom Page viii Document AC101 DS01 405 R...

Page 9: ...2 PHY Identifier 1 Register 26 Table 17 Register 3 PHY Identifier 2 Register 26 Table 18 Register 4 Auto Negotiation Advertisement Register 26 Table 19 Register 5 Auto Negotiation Link Partner Abilit...

Page 10: ...Characteristics 37 Table 39 Power On Reset Timing 39 Table 40 Management Data Interface Timing 39 Table 41 100BASE TX FX MII Transmit System Timing 40 Table 42 100BASE TX FX MII Receive System Timing...

Page 11: ...device can operate in 10 or 100 Mbps with full duplex or half duplex mode MAC INTERFACE MEDIA INDEPENDENT INTERFACE MII The Media Independent Interface MII is an 18 wire MAC PHY interface see MII Medi...

Page 12: ...be asserted when ever one of 8 selectable interrupt events occur Assertion state is programmable to either high or low through the INTR_LEVL register bit see Register 16 Polarity and Interrupt Level R...

Page 13: ...ANeg the PHY will support all the features and parameters of the industry standards Transmit Function If the MII interface is used Parallel to Serial logic is used to convert the 4 bit data into the s...

Page 14: ...sequence for each PHY i e the scrambled seed is unique for each different PHY based on the PHY address When Dis_Scrm see Register 21 Mode Control Register on page 32 is set to 0 the data scrambling f...

Page 15: ...will switch and lock on to TX_CLK This provides a continuously running RX_CLK At the PCS interface the 5 bit data RXD 4 0 is synchronized to the 25 MHz RX_CLK See MII Media Independent Interface 100...

Page 16: ...t entity sets the transmit Far End Fault bit The FEFI mechanism is enabled by default in the 100BASE FX mode and is disabled in 100BASE TX or 10BASE T modes The register setting can be changed by soft...

Page 17: ...jabber timer 46mS the transmit and loopback functions will be disabled and COL signal get asserted After TX_EN goes low for more than 500 ms the TP transmitter will reactivate and COL gets de assert e...

Page 18: ...on mechanism defined in the clause 28 of IEEE 802 3u specification ANeg can be enabled or disabled by hardware ANEGA pin or soft ware Reg 0 12 control When the ANeg is enabled the PHY chooses its mode...

Page 19: ...tion DIAGNOSTICS Loopback Operation Local Loopback and Remote Loopback are provided for testing purpose They can be enabled by write to either Reg 0 14 LPBK or Reg 21 3 EN_RPBK See Register 0 Control...

Page 20: ...s no live network connected Energy Detect ED circuit is always turned on to monitor if there is a signal energy present on the media The management circuitry is also powered on and ready to respond to...

Page 21: ...og signal Active Low Signal NC No Connect pin P Power G Ground PIN DESCRIPTIONS PHY ADDRESS PINS MDI MEDIA DEPENDENT INTERFACE PINS Table 1 PHY Address Pins Pin Name 101TF 101QF Type Description PHYAD...

Page 22: ...ta is present on the RX 3 0 In 100Base mode it is asserted with the first nibble of preamble and is de asserted when the last data nibble has been received In 10Base mode it is asserted when the SFD S...

Page 23: ...1TF 101QF Type Description TP_RD TP_RD TP_TD TP_TD TP_TD TP_TD 14 15 16 19 17 18 19 20 21 24 22 23 I O U I O U I U I U I U I U 10BASE T serial input and output The ANeg function is disabled there fore...

Page 24: ...etting MII Reg 0 11 see Register 0 Control Register on page 24 RIBB 72 92 A Reference Bias Resistor To be tied to analog ground through an exter nal 10 0 K 1 resistor CKIN 5 10 I D Clock Input Connect...

Page 25: ...Reg 1 3 ACTIVITY 56 71 I U Activity In PCS bypass mode PCSBP pin pull high the MAC provides the activity signal to generate the activity LED signal RPTR 61 81 I Repeater Mode When this pin is asserted...

Page 26: ...CRAM_EN When this pin is pulled low via 1 K during reset the scrambler de scrambler function will be disabled LEDRX LEDSEL 46 61 I O U LEDRX Receive LED This pin will toggle between high and low when...

Page 27: ...rives a 100B T status LED The LEDTXA B pin is enabled if the LED SEL pin is pulled low during reset See Advanced LED Selections on page 19 Table 9 Power and Ground Pins 101TF 101QF Type Description Po...

Page 28: ...Decide by SMI input Writeable 0 001 0001 0001 0 Not Write able 0 Not Write able 0 01x 0100 0100 1 Not Write able 0 Not Write able 0 101 0010 0010 0 Not Write able 1 Not Write able 0 11x 1000 1000 1 N...

Page 29: ...Off 0 0 Off 10B T HDX Link 1 0 Yellow 0 0 Off 10B T HDX RX Flashing 0 Yellow 0 0 Off 10B T FDX DX Link 0 1 Green 0 0 Off 10B T FDX RX 0 Flashing Green 0 0 Off 100B TX HDX Link 0 0 Off 1 0 Yellow 100B...

Page 30: ...ections Document AC101 DS01 405 R A suggested LED connection diagram is shown in Figure 3 that could simplify the board design Figure 3 Dual color LED Indicator for Link Duplex and Activity Status 10B...

Page 31: ...NC NC NC ISODEF ISO GNDT CKIN NC CLK25 BURN_IN RST PWRDN VAAPLL OGND GNDPLL PHYAD 4 TP_RD PHYAD 3 TP_RD OVDD PHYAD 2 TP_TD PHYAD 1 TP_TD PHYAD 0 TP_TD GPIO 0 TP_TD 7W GPIO 1 TP125 81 82 83 84 85 86 8...

Page 32: ...XON VAAT VAAT PCSBP ISODEF ISO GNDT CKIN NC CLK25 BURN_IN RST PWRDN VAAPLL OGND GNDPLL PHYAD 4 TP_RD PHYAD 3 TP_RD OVDD PHYAD 2 TP_TD PHYAD 1 TP_TD PHYAD 0 TP_TD GPIO 0 TP_TD 7W GPIO 1 TP125 61 62 63...

Page 33: ...to registers it is recommended that a read modify write operation be performed as unin tended bits may get set to unwanted states This applies to all registers including those with reserved bits Tabl...

Page 34: ...2 0 0 12 ANeg Enable 1 Enable Auto Negotiate process overrides 0 13 and 0 8 0 Disable Auto Negotiate process Mode selection is con trolled via bit 0 8 0 13 or through TECH 2 0 pins see Con trol and St...

Page 35: ...10BaseT full duplex capable RO TECH 2 0 1 11 10BASE T Half duplex 1 10BaseT half duplex capable 0 Not 10BaseT half duplex capable RO TECH 2 0 1 10 7 Reserved RO 0000 1 6 MF Preamble Suppression The P...

Page 36: ...Y Identifier 2 Register Reg bit Name Description Mode Default 3 15 10 OUIa a Based on an OUI of 0010A9 Hex Assigned to the 19th through 24th bits of the OUI RO 010101 3 9 4 Model Number Six bit manufa...

Page 37: ...transfer 0 Link partner does not desire Next Page transfer RO 0 5 14 Acknowledge 1 Link Partner acknowledges reception of FLP words 0 Not acknowledged by Link Partner RO 0 5 13 Remote Fault 1 Remote F...

Page 38: ...ault detected by parallel detection logic RO LH 0 6 3 Link Partner Next Page Able 1 Link partner supports next page function 0 Link partner does not support next page function RO 0 6 2 Next Page Able...

Page 39: ...gnal of GPIO 1 pin When GPIO 1 DIR bit is set to 0 the value of this bit will dis play on GPIO 1 pin RW 0 16 8 GPIO 1 DIR Set to one then GPIO 1 pin is input Set to zero then GPIO 1 pin is an output R...

Page 40: ...new page is received during ANeg RC 0 17 4 PD_Fault_Int This bit is set when parallel detect fault is detected RC 0 17 3 LP_Ack_Int This bit is set when the FLP with acknowledge bit set is re ceived...

Page 41: ...loopback 1 Enable loopback 0 Normal operation RW 0 19 2 LP_LPBK 1 Enable link pulse loopback 0 Normal operation RW 0 19 1 NLP Link Integ rity Test 1 In ANeg test mode send NLP instead of FLP in order...

Page 42: ...peater mode RW 0 21 9 LED_Sel 1 Use the LED configuration which is compatible with TSC78Q2120 0 Select LED selection see Advanced LED Selections on page 19 RW Set by LED_RX LEDSEL 21 8 FEF_Disable 1 D...

Page 43: ...3 2 1 0 SYMBOL Name MII TXD RXD 3 0 3 2 1 0 Description 11110 0 0000 Data 0 01001 1 0001 Data 1 10100 2 0010 Data 2 10101 3 0011 Data 3 01010 4 0100 Data 4 01011 5 0101 Data 5 01110 6 0110 Data 6 011...

Page 44: ...HALT code group 00000 V Undefined Invalid code 00001 V Undefined Invalid code 00010 V Undefined Invalid code 00011 V Undefined Invalid code 00101 V Undefined Invalid code 00110 V Undefined Invalid co...

Page 45: ...otal Power Consumption Parameter Symbol Conditions Min Typ Max Units Supply Current Icc 10BASE T Idle 10BASE T Normal activity 100BASE TX 100BASE FX 10 100BASE TX low power without ca ble Power down 2...

Page 46: ...cteristics Parameter Symbol Conditions Min Typ Max Units Output Low Voltage Vol 0 4 V Output High Voltage Voh 2 4 V Input Current Ii 8 8 A Output Current Io 10 10 mA Table 35 100BASE TX Transceiver Ch...

Page 47: ...Current High Ioh 1 1 Transformer 100 mA Output Current High Ioh 1 25 1 Transformer 80 mA Start of Idle Pulse Width 300 350 ns Output Jitter 1 4 ns Receive Jitter Tolerance 32 ns Receive Input Imped a...

Page 48: ...olt age High Vih 2 1 2 4 V Differential Output Volt age Low Vil 1 5 1 8 V Output Current Sink 15 16 mA Table 38 Parameter Symbol Conditions Min Typ Max Units Time Link Loss Receiv er 50 150 ms Link Pu...

Page 49: ...t Timing MANAGEMENT DATA INTERFACE TIMING Table 39 Power On Reset Timing Parameter SYM Conditions Min Typ Max Units RST Low Period tRST 150 s Configuration tCONF 100 ns Table 40 Management Data Interf...

Page 50: ...2 000 ns TX_CLK Low period tCKL 18 000 20 000 22 000 ns TX_EN to J tTJ 40 180 ns TX_EN sampled to CRS tCSA RPTR is logic low 40 180 ns TX_EN sampled to COL tCLA RPTR is logic low 40 180 ns TX_EN to T...

Page 51: ...CLK Low period tCKL 18 000 20 000 22 000 ns J K to RX_DV assert tRDVA 40 180 ns J K to CRS assert tRCSA 40 180 ns J K to COL assert tRCLA RPTR is logic low 40 180 ns T R to RX_DV tRDVD RPTR is logic l...

Page 52: ...eter SYM Conditions Min Typ Max Units TX_CLK period tCK 399 98 400 00 400 02 ns TX_CLK High period tCKH 180 00 200 00 220 00 ns TX_CLK Low period tCKL 180 00 200 00 220 00 ns TX_EN to SOP tTJ 240 360...

Page 53: ...sampled to COL tTCLD RPTR is logic low 300 ns TX Propagation Delay tTJ From TXD 3 0 to TXOP N 240 360 ns TXD 3 0 TX_EN TX_ER Setup tTXS From rising edge of TX_CLK 10 ns TXD 3 0 TX_EN TX_ER Hold tTXH...

Page 54: ...0 00 220 00 ns CRS to RX_DV tRDVA 100 100 100 ns SOP to CRS tRCSA 80 150 ns SOP to COL tRCLA RPTR is logic low 80 150 ns EOP to RX_DV tRDVD RPTR is logic low 120 140 ns EOP to CRS tRCSD RPTR is logic...

Page 55: ...iod tCKH 45 00 50 00 55 00 ns 10TCLK Low period tCKL 45 00 50 00 55 00 ns 10TXEN to SOP tTJ 240 360 ns 10TXEN sampled to 10CRS tTCSA RPTR is logic low 130 ns 10TXEN to EOP tTJ 240 360 ns 10TXEN sample...

Page 56: ...KH 45 00 50 00 55 00 ns 10RCLK Low period tCKL 45 00 50 00 55 00 ns SOP to 10CRS tRCSA 750 850 ns 10CRS to 10RD tRDVA 750 850 ns EOP to 10CRS tRCSD 750 850 ns RX Propagation Delay tRDVD From RXOP N to...

Page 57: ...ase contact Altima Communications Inc for the latest component value recommendation Figure 15 TX Application Termination Circuit 10COL tCCD tCCA RXIP N TXON TXOP RIBB RXIP RXIN 1 TX 2 TX 3 RX 4 Unused...

Page 58: ...st component value recommendation To enable the FX mode FX_DIS pin see LED Indicators Pins on page 16 must be pulled low by a 1 kilohm resistor Figure 16 FX Application Termination Circuit SDP FXRN FX...

Page 59: ...latest component value recommendation Figure 17 Power and Ground Filtering for the AC101QF AC101QF 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 85 GNDEQ 91 GNDREF 93 VAAREF 96 GNDT 99 VAAT 100 VAAT 9 GNDT 15 VAA...

Page 60: ...unications Inc for the latest component value recommendations Figure 18 Power and Ground Filtering for the AC101TF AC101TF 1u 1u 1u 65 GNDEQ 71 GNDREF 73 VAAREF 76 GNDT 79 VAAT 80 VAAT Components plac...

Page 61: ...Page 51 Section 7 Mechanical Information PACKAGE DIMENSIONS FOR AC101QF 100 PIN PQFP Figure 19 Package Dimensions for AC101QF 100 pin PQFP Table 48 Quad Flat Pack Outline 20 x 14 mm N A A1 A2 B D D1 E...

Page 62: ...nt AC101 DS01 405 R PACKAGE DIMENSIONS FOR AC101TF 80 PIN TQFP Figure 20 Package Dimensions for AC101TF 80 pin TQFP Table 49 Quad Flat Pack Outline 12 x 12 mm N A A1 A2 B D D1 E E1 e L L1 80 1 20 Max...

Page 63: ...Preliminary Data Sheet AC101 06 04 01 Broadcom Document AC101 DS01 405 R Page 53...

Page 64: ...e to any products or data herein to improve reliability function or design Information furnished by Broadcom Corporation is believed to be accurate and reliable However Broadcom Corporation does not a...

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