Altima AC101 Series, Manual, Page: 39 / 64

Preliminary Data Sheet
■
AC101
06/04/01
B r o a d c o m
Document AC101-DS01-405-R¥¥¥¥¥ MII-Specified Registers Page 29
A
LTIMA
-S
PECIFIED
R
EGISTERS
R
EGISTER
16: P
OLARITY AND
I
NTERRUPT
L
EVEL
R
EGISTER
Table 22: Register 16: Polarity and Interrupt Level Register
Reg.bit Name Description Mode Default
16.15 Repeater • 1= Repeater mode, full-duplex will be inactive, and CRS
only responses to receive activity. SQE test function is dis-
abled.
RW Set by
RPTR
16.14 INTR_LEVL • 1=INTR pin will be active high.
• 0=INTR pin will be active low.
RW 0
16.[13:12] Reserved RW 00
16.11 SQE Test
Inhibit • 1 = Disable 10BaseT SQE testing.
• 0 = Enable 10BaseT SQE testing, which will generate a COL
pulse following the completion of a packet transmission.
RW 0
16.10 10BaseT
Loopback • 1 = Enable normal loopback in 10BaseT mode.
• 0 = Disable normal loopback in 10BaseT mode.
RW 1
16.9 GPIO[1] Data • When GPIO[1] DIR bit (Reg. 16.8) is set to one, this bit value
reflects the signal of GPIO[1] pin.
• When GPIO[1] DIR bit is set to 0, the value of this bit will dis-
play on GPIO[1] pin.
RW 0
16.8 GPIO[1] DIR • Set to one then GPIO[1] pin is input.
• Set to zero then GPIO[1] pin is an output.
RW 1
16.7 GPIO[0] Data When GPIO[0] DIR (Reg. 16.6) bit is set to one, this bit value
reflects the signal of GPIO[0] pin. When GPIO[0] DIR bit is set
to 0, the value of this bit will display on GPIO[0] pin. RW 0
16.6 GPIO[0] DIR • Set to one then GPIO[0] pin is input.
• Set to zero then GPIO[0] pin is an output.
RW 1
16.5 Auto Polarity
Disable • 1 = Disable Auto Polarity detection/correction.
• 0 = Enable Auto Polarity detection/correction.
RW 0
16.4 Reverse Polari-
ty • 1= Reverse Polarity when Reg. 16.5 = 0.
• 0= Normal Polarity when Reg. 16.5 = 0.
If Reg. 16.5 is set to 1, writing a one to this bit will reverse the
polarity of the transmitter.
RW 0
16.[3:1] Reserved RO 000
16.0 Receive Clock
Control Writing a one to this bit will shut off RX_CLK when incoming
data is not present. RX_CLK will resume 1 clock cycle prior to
RX_DV going high, and shut off 64 clock cycles after RX_DV
goes low.
No action when in Loopback or PCS Bypassed modes.
RW 0