Altima AC101 Series, Manual, Page: 42 / 64

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AC101 Preliminary Data Sheet
06/04/01
B r o a d c o m
Page 32 MII-Specified Registers Document AC101-DS01-405-R¥¥¥¥¥
R
EGISTER
21: M
ODE
C
ONTROL
R
EGISTER
Table 27: Register 21: Mode Control Register
Reg.bit Name Description Mode Default
21.15 Reserved RO 0
21.14 NLP Disable • 1 = Force 10B-T link up without checking NLP.
• 0 = Normal Operation.
RW 0
21.13 Force_link_up • 1 = Ignore link in 100BASE-TX and transmit data. ANeg
must be disabled at this time (ANEGA pin tied low).
• 0 = Normal Operation.
RW 0
21.12 Jabber Disable • 1 = Disable Jabber function in PHY.
• 0 = Enable Jabber function in PHY.
RW 0
21.11 10BT_Sel • 1 = Enable 7-wire interface for 10BASE-T operation.
• 0 = Normal operation. (Not valid in PCS Bypass mode.)
RW 0
21.10 Conf_ALED • 1 = Activity LED only responds to receive operation.
• 0 = Activity LED responds to receive and transmit.
This bit should be ignored when Reg. 0.8 (see ”Register 0:
Control Register” on page 24) is set or in the repeater mode.
RW 0
21.9 LED_Sel • 1 = Use the LED configuration which is compatible with
TSC78Q2120.
• 0 = Select LED selection (see ”Advanced LED Selections”
on page 19).
RW Set by
LED_RX/
LEDSEL
21.8 FEF_Disable • 1 = Disable Far End Fault Insertion.
• 0 = Enable Far End Fault Insertion and detection function.
This bit valid when FX mode is enabled.
RW Set by
TECH,
FX_DIS,
ANEGA
21.7 Force FEF
Transmit • 1 = Force transmission of Far End Fault Insertion pattern.
• 0 = Normal operation.
RW 0
21.6 Rx_Er_Cnt Full • 1 = Receive Error Counter full.
• 0 = Receive Error Counter not full.
RO/ RC 0
21.5 Disable
Rx_Er_Cnt • 1 = Disable Receive Error Counter.
• 0 = Enable Receive Error Counter.
RW 0
21.4 Dis_WDT • 1 = Disable the watchdog timer in the decipher.
• 0 = Enable watchdog timer.
RW 0
21.3 En_RPBK • 1 = Enable remote loopback.
• 0 = Disable remote loopback.
RW 0
21.2 Dis_Scrm • 1 = Enable 100M data scrambling.
• 0 = Disable 100M data scrambling.
When FX mode is selected, this bit will be forced to zero.
RW Set by
LED_COL/
SCRAM_EN
21.1 PCSBP • 1 = Bypass PCS. Disable 4b/5b and scrambler in 100B-TX
mode.
• 0 = Enable PCS. Enable 4b/5b and scrambler in 100B-TX
mode.
RW Set by
PCSBP