Preliminary Data Sheet
■
AC101
06/04/01
B r o a d c o m
Document AC101-DS01-405-R¥¥¥¥¥
Overview
Page 1
S e c t i o n 1 : F u n c t i o n a l D e s c r i p t i o n
O
VERVIEW
The AC101TF/QF PHYsical layer device (PHY) integrates the 100BASE-X and 10BASE-T functions in a single chip that is
used in Fast Ethernet 10/100 Mbps applications. The 100BASE-X section consists of physical coding sublayer (PCS), phys-
ical media attachment (PMA), and physical media dependent (PMD) functions and the 10BASE-T section consists of
Manchester encoder/decoder (ENDEC) and transceiver functions. The device performs the following functions:
•
4B/5B
•
MLT3
•
NRZI
•
Manchester Encoding and Decoding
•
Clock and Data Recovery
•
Stream Cipher Scrambling/De-Scrambling
•
Adaptive Equalization
•
Line Transmission
•
Carrier Sense
•
Link Integrity Monitor
•
Auto-Negotiation (ANeg)
•
MII MAC connectivity
•
MII Management Function
It also provides an IEEE802.3u compatible Media Independent Interface (MII) to communicate with an Ethernet Media Ac-
cess Controller (MAC). Selection of 10 or 100 Mbps operation is based on the settings of internal Serial Management Inter-
face registers or determined by the on-chip ANeg logic. The device can operate in 10 or 100 Mbps with full-duplex or half-
duplex mode.
MAC I
NTERFACE
M
EDIA
I
NDEPENDENT
I
NTERFACE
(MII)
The Media Independent Interface (MII) is an 18 wire MAC/PHY interface (see ”MII (Media Independent Interface) 100 PCS
Bypass Pins” on page 12) described in 802.3u. The purpose of the interface is to allow MAC layer devices to attach to a
variety of Physical Layer devices through a common interface. MII operates at either 100 Mbps or 10 Mbps, dependant on
the speed of the Physical Layer. With clocks running at either 25 MHz or 2.5 MHz, 4 bit data is clocked between the MAC
and PHY, synchronous with Enable and Error signals.
At the time of PLL lock on an incoming signal from the wire interface, the PHY will generate RX_CLK at either 2.5 MHz for
10 Mbps or 25 MHz for 100 Mpbs.
On receipt of valid data from the wire interface, RX_DV will go active signaling to the MAC that the valid data will be present-
ed on the RXD[3:0] pins at the speed of the RX_CLK.
On transmission of data from the MAC, TX_EN is presented to the PHY indicating the presence of valid data on TXD[3:0].
TXD[3:0] are sampled by the PHY synchronous to TX_CLK during the time that TX_EN is valid.
Serial Management Interface (SMI)
The PHY’s internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI. see ”MII (Media