ADMtek ADM5120, Datasheet, Page: 96 / 112

ADM5120 Register Description
Bit # Type Name Descriptions Initial Value
00000 to 11110 = (n+2) HCLK cycle write access time
11111 = 33 HCLK cycle write access time (reset value
on nPOR).
31:5 Reserved Read undefined, must be written as zeros.
Note:
The wait state time for write accesses after the first read is WAITWR x tHCLK.
4.7.27 MPMC Static Wait Turn [0,1,2,3] register
Note:
offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name Descriptions Initial Value
3:0 R/W WAITTURN Bus turnaround cycles:
0000 to 1110 = (n+1) HCLK turnaround cycles
1111 = 16 HCLK turnaround cycles (reset value on
nPOR). 1111
31:4 Reserved Read undefined, must be written as zeros.
Note:
Bus turnaround time is (W1) x tHCLK.
4.7.28 Conceptual MPMC Additional Peripheral ID register
Bit # Type Name Descriptions Initial Value
7:0 R Configuration1 Additional peripheral configuration information. 0
31:8 W Reserved Read undefined, must be written as zeros. 0
Note:
The configuration options are peripheral-specific. For MPMC, the four, eight-bit
peripheral identification registers are described in the following sections:
4.7.29 MPMC PeriphID4 register, offset FD0h
Bit # Type Name Descriptions Initial Value
0 R Configuration Static memory interface:
0=no
1=yes (value for PL172). 1
2:1 R Configuration Number of read/write buffers:
00=4 buffers (value for PL172)
01=8 buffers
10=12 buffers
11=16 buffers..
00
31:3 Reserved Read undefined, must be written as zeros.
Note:
ADMtek Inc. 4-49
The MPMCPeriphID4 register is hard-coded and the fields within the register determine
the reset value.