ADM5120
Register Description
4.7.8 MPMC Dynamic RAS register, offset 034h
Bit # Type Name
Descriptions
Initial Value
3:0
R/W tRAS
Active to precharge command period:
0x0 to 0xE = n+1 clock cycle
0xF = 16 clock cycles (reset value on nPOR).
0xF
31:4
Reserved
Read undefined, must be written as zeros.
Note:
The delay is in MPMCCLK cycles.
4.7.9 MPMC Dynamic SREX register, offset 038h
Bit # Type Name
Descriptions
Initial Value
3:0
R/W
tSREX
Self-refresh exit time:
0x0 to 0xE = n+1 clock cycle
0xF = 16 clock cycles (reset value on nPOR).
0xF
31:4
Reserved
Read undefined, must be written as zeros.
Note:
The delay is in MPMCCLK cycles.
4.7.10 MPMC Dynamic APR register, offset 03Ch
Bit # Type Name
Initial Value
R/W
tAPR
0x0 to 0xE = n+1 clock cycle
0xF = 16 clock cycles (reset value on nPOR).
0xF
31:4
Reserved
Read undefined, must be written as zeros.
Descriptions
3:0
Last-data-out to active command time:
Note:
The delay is in MPMCCLK cycles.
4.7.11 MPMC Dynamic DAL register, offset 040h
Bit # Type
Descriptions
Initial Value
R/W tDAL
Data-in to active command time:
0x0 to 0xE = n+1 clock cycle
0xF = 16 clock cycles (reset value on nPOR).
0xF
31:4
Reserved
Read undefined, must be written as zeros.
Name
3:0
Note:
The delay is in MPMCCLK cycles.
4.7.12 MPMC Dynamic WR register, offset 044h
Bit # Type
Descriptions
Initial Value
3:0
R/W tWR
Write recovery time:
0x0 to 0xE = n+1 clock cycle
0xF = 16 clock cycles (reset value on nPOR).
0xF
31:4
Reserved
Read undefined, must be written as zeros.
Name
ADMtek Inc.
4-41
Note:
The delay is in MPMCCLK cycles.