ADM5120
Product Overview
1.2 Features
ASIC Features
Processor
– Two bank support (2 chip
select pins)
•
MIPS 4Kc CPU
– Each bank can support --
1Mx32 up to 32Mx32bit
(128M-byte)
•
Embedded cache, 8K-byte I-
cache, 8K D-cache
•
Embedded memory management
unit (MMU) – 32-entry TLB,
organized as 16 entry pairs
•
Flash
– NAND Flash boot (
*
)
•
175 MHz/227 MIPS
– NOR
Flash
boot:
Two
bank support (2 chip
select pins)
Network
– NOR Flash boot: Each
bank can support –
1Mx8-bit, up to 1Mx32-
bit (4M-byte)
•
6 ports
– IEEE 802.3 Fast Ethernet
– 5 auto-MDIX (auto-
crossover) twisted paired
LAN interfaces,
embedded 10/100M PHY
System
– 1
GMII(
*
)/MII interface
•
UART interface (support
MODEM interface)
– Flexible
WAN
port
selection
•
PCI bridge that supports 3 master
devices (
*
)
•
Embedded switch engine
•
GPIO (
**
)
– Embedded
Data-
buffer/Address-look-up
table
•
USB 1.1 host
•
Clock source
o
25MHz crystal for 10/100
– Look-up table read/write-
able
o
48MHz crystal for USB
– MAC
layer
security
•
0.18u CMOS process
– MAC clone solution
•
1.8V/3.3V dual power
– Multicast
grouping
(IGMP)
•
BGA/PQFP
– MAC
filtering,
Bandwidth control
VPN interface toADM5001
•
Class of Services (CoS) with two
priority levels
* Available in BGA only, not PQFP
** PQFP has 4 GPIO pins v.s. BGA
has 8 pins.
•
Shared dynamic data buffer
management, embedded SSRAM
•
Port grouping VLAN (overlap-
able)
•
TCP/IP accelerator
Memory interface
•
SDRAM
ADMtek Inc.
1-2