ADMtek ADM5120 Datasheet Download Page 54

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ADM5120

D_bist_fail

Data buffer BIST result

→

0: Pass

L_bist_fail

Link table BIST result

→

0: Pass

MC_bist_fail

MC table BIST result

→

0: Pass

AT_bist_fail

address table BIST reseult

→

0: Pass

5:4

Dcache_D_test_fail Bit 5 and Bit 4 are respectively for the upper and lower

32-bit of D-cache memory for data

→

00: Pass

Dcache_T_test_fail the memory of D-cache tag

→

0: Pass

8:7

Icache_D_test_fail Bit 8 and Bit 7 are respectively for the upper and lower

32-bit of I-cache memory for data

→

00: Pass

9 RO

Icache_T_test_fail

the memory of I-cache tag

→

0: Pass

10 RO

all_mem_test_done

all embedded memory test completed

→

1: complete

19:11 RO skip_blocks

the number of block is skipped up to 64 blocks

21 RO Dcache_portion

For debugging purpose of embedded SRAM

22 RO Icache_portion

For debugging purpose of embedded SRAM

31:23

Reserved

Not

Applicable

4.4.6 PHY_St, offset: 0x14

Bits

Type Name

Description

Initial value

4:0 RO Link

PHY

Link

→

1=up, 0=down

5 RO

MII_fail

→

MII, 1=link ok, 0= port fail

7:6

Reserved

Not

Applicable

12:8 RO Speed

Speed

→

1=100M, 0=10M

14:13

GMII_speed

GMII port speed

→

10: giga(disable on PQFP),

01:100M, 00: 10M

15 Reserved

Not

Applicable

21:16 RO Duplex

Duplex

→

1= full duplex, 0=half duplex

23:22

Reserved

Not

Applicable

28:24 RO FC_st

→

1 = full duplex and 802.3x flow control ON (after

AN or forced)

30:29

GMII_FC_st

FC status of GMII port

→

[29]=1, FC on if 10/100M,

RX_FC on if giga, [30]=1, TX_FC on if giga

31 Reserved

Not

Applicable

4.4.7 Port_St, offset: 0x18

Bits

Type Name

Description

Initial value

5:0 RO Secured_st

Security

status

→

1= has intruder coming if turn on the

SA_securd mode

6 Reserved

Not

Applicable

7 RO

TXC_st

→

MII port TXC status, 1= error, no TXC or

too long period

31:8

Reserved

Not

Applicable

ADMtek Inc.

4-7

Summary of Contents for ADM5120

Page 1: ...future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products may contain design defects or errors known as errata w...

Page 2: ...er 2 Interface Description Chapter 3 Function Description Chapter 4 Register Description Chapter 5 Electrical Packaging Chapter 6 Packaging Customer Support ADMtek Incorporated 2F No 2 Li Hsin Rd Scie...

Page 3: ...d pin numbers 13 June 2003 1 11 Updated Table for Clock Speeds 08 October 2003 1 12 2 2 5 Memory Bus A 2 2 2 10 PCI added CLK I P 2 2 11 USB added CLK I P 2 2 14 Corrected pin name 2 2 15 Changed I to...

Page 4: ...a Connection 2 5 2 2 2 Clock for Network 2 5 2 2 3 LED 2 5 2 2 4 GMII MII Management 2 6 2 2 5 Memory Bus 2 7 2 2 6 SDRAM Control Signals 2 8 2 2 7 UART 2 8 2 2 8 JTAG 2 9 2 2 9 General Purpose I O GP...

Page 5: ...3 10 3 4 3 Operational Register 3 10 3 4 4 SIE 3 11 3 4 5 DPLL 3 11 3 4 6 Memory BIST 3 11 3 5 DMA OPERATION 3 11 3 5 1 Endpoint Descriptor Format 3 11 3 5 2 Transfer Descriptor Format 3 12 3 5 3 DMA...

Page 6: ...ffset 0x48 4 13 4 4 20 Srch_cmd offset 0x4c 4 13 4 4 21 ADDR_st0 offset 0x50 4 14 4 4 22 ADDR_st1 offset 0x54 4 14 4 4 23 MAC_wt0 offset 0x58 4 14 4 4 24 MAC_wt1 offset 0x5c 4 14 4 4 25 BW_cntl0 offse...

Page 7: ...68 port3_LED offset 0x10c 4 26 4 4 69 port4_LED offset 0x110 4 26 4 5 USB CONTROL STATUS REGISTER MAP 4 26 4 6 USB CONTROL STATUS REGISTERS DESCRIPTION 4 27 4 6 1 General Control offset 0x00 4 27 4 6...

Page 8: ...1 2 3 register 4 49 4 7 28 Conceptual MPMC Additional Peripheral ID register 4 49 4 7 29 MPMC PeriphID4 register offset FD0h 4 49 4 7 30 MPMC PeriphID5 7 register offset FD4h FD8h FDCh 4 50 4 7 31 Con...

Page 9: ...IONS 5 1 5 3 AC TIMING 5 2 5 3 1 SDRAM interface 5 2 5 3 2 Memory Bus Read Timing 5 5 5 3 3 Memory Bus Write Timing 5 6 CHAPTER 6 PACKAGING 6 1 6 1 BALL GRID ARRAY BGA 324 PIN 6 1 ADM5120 vi 6 2 PLAST...

Page 10: ...gure 4 1 System Memory Map 4 1 Figure 5 1 Precharge Command 5 2 Figure 5 2 Active Command 5 3 Figure 5 3 Write Command 5 4 Figure 5 4 Read Command 5 4 List of Tables Table 2 1 ADM5120 324 BGA Pin Assi...

Page 11: ...e ADM5120 ASIC consists of a high performance 227 MIPS embedded MIPS CPU an embedded switch engine 10 100M PHY an embedded PCI bridge an embedded USB host and interfaces for UART SDRAM Flash and VPN e...

Page 12: ...0 100M PHY System 1 GMII MII interface UART interface support MODEM interface Flexible WAN port selection PCI bridge that supports 3 master devices Embedded switch engine GPIO Embedded Data buffer Add...

Page 13: ...IEEE 802 11 WLAN Driver Multiple band 802 11a b g Access Point through PCI bus 5120 802 11a b g NIC RS232 Driver for Console User Interface DHCP Server Client Print Server through USB1 1 PPP over Eth...

Page 14: ...100 auto MDIX PHY DSP port DMA TX RX GMAC GMII MII external chip select PCI bridge PCI bus UART i f UART USB host USB USB embedded addr table Figure 1 1 ADM5120 Block Diagram 1 4 Abbreviations AHB Ad...

Page 15: ...ata I O MDI Medium dependent interface MDIX MDI Crossover MII Media Independent Interface MIPS Million Instructions Per Second MMU Memory Management Unit NAT Network Address Translation NRZI Non Retur...

Page 16: ...ea Networks 1 5 Conventions 1 5 1 Data Lengths qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits 1 5 2 Register Descriptions Register Type Description RO Read only WO Write only RW Re...

Page 17: ...V9 22 UDSR P18 22 TXN4 C10 23 G_TXE H2 23 PCI_AD 24 U9 23 UCTS L17 23 TXP4 B9 24 G_RXC J1 24 ADDR 10 W9 24 UDI0 R20 24 VCCA2 A9 25 G_RXDV K4 25 ADDR 7 Y9 25 UDO0 N18 25 VCCA2 A8 26 G_RXD 0 J2 26 ADDR...

Page 18: ...64 DATA 27 V3 64 VSS Y3 64 GPIO 5 C19 64 VDD H4 65 DATA 26 Y2 65 VSS N8 65 GPIO 6 D18 65 VDD K17 66 DATA 25 W3 66 VSS N9 66 GPIO 7 E17 66 VDD P16 67 PCI_CBE 0 U4 67 VSS M8 67 TEST C18 67 68 68 VSS K8...

Page 19: ...ADM5120 Interface Description 2 1 2 208PQFP pin assignment ADMtek Inc 2 3 Table 2 2 ADM5120 208PQFP Pin Assignments...

Page 20: ...nnection Section 2 2 2 Clock for Network Section 2 2 3 LED Section 2 2 4 GMII MII Management Section 2 2 5 Memory Bus Section 2 2 6 SDRAM Control Signals Section 2 2 7 UART Section 2 2 8 JTAG Section...

Page 21: ...Clock for Network Pin Name BGA Ball PQFP Pin Type Descriptions XOI H5 9 O 25 MHz crystal XI G4 10 I 25 MHz crystal external clock input RTX C2 3 I Reference Voltage 2 2 3 LED ADMtek Inc 2 5 Pin Name...

Page 22: ...nction State GPIO_in or GPIO_disable 0000 GPIO_output_flash 0001 GPIO_output_0 0010 GPIO_output_1 0011 link steady 0100 speed steady 0101 duplex steady 0110 activity flash 0111 collision flash 1000 li...

Page 23: ...I Receive Data internal pull down 2 2 5 Memory Bus Pin Name BGA Ball PQFP Pin Type Descriptions DATA 31 0 P5 U1 W1 V2 V3 Y2 W3 V5 T4 U3 W2 Y1 T1 R4 R3 P3 W18 T17 V17 U16 V15 Y16 W15 T14 W12 W14 Y15 U1...

Page 24: ...DRAM_CS0_N U8 64 O SDRAM chip select 1 RAS_N T8 60 O Raw address strobe active low CAS_N V6 59 O Column address strobe active low SDRAM_CS1_N W5 58 O SDRAM chip select 1 DQM 3 0 T11 U12 T7 Y4 83 84 55...

Page 25: ...IO 0 is internal pull up GPIO 2 1 are internal pull down Note In the BGA version GPIO5 can be programmed to SDRAM memory address A20 for 2Mx16bit Flash thus supporting large Flash memory LEDN 2 0 Refe...

Page 26: ...a of USB port1 differential data bus conforming to the USB 1 1 DPLS1 B12 172 BI Data of USB port1 differential data bus conforming to the USB 1 1 DMNS0 C11 175 BI Data of USB port0 differential data b...

Page 27: ...G17 150 I External interrupt input active high available if en_csx_intx enable in the switch control register GPIO_config2 B BC bit 4 CSX_1 E18 151 O External chip select 1 active low available if en_...

Page 28: ...0 K9 B2 A1 A2 A3 A4 C6 D5 E8 H8 J8 L8 M9 M11 M12 W20 N13 M13 L11 L12 K13 J11 J12 J13 K11 K12 L13 7 11 21 32 39 45 53 61 69 78 77 87 93 94 103 104 111 112 126 132 138 156 157 167 GND for Digital circui...

Page 29: ...ian default 0 little endian x00 boot in 8 bit default x01 boot in 16 bit x10 boot in 32 bit 11 Reserved 3 1 3 GMII MII port The GMII MII port can be programmed for the following AN monitor on off forc...

Page 30: ...tion is implemented in the device logic Similarly in the 10BASE T mode Manchester encoding and decoding is used with two level transmitted and received data on CAT 3 cable 3 2 2 Link Detect The 10Base...

Page 31: ...ing point to the optimum position This recovered clock is used to synchronize all other functions of the Receive section especially data recovery and data transmittal 3 2 6 Stream Cipher Scrambler De...

Page 32: ...t 5 The packets from CPU 3 3 3 Routing When a packet comes from portA ADM5120 will compare its destination MAC address with the MAC address in the MAC address lookup table If the address is the same a...

Page 33: ...to prevent the packet lost 3 3 7 Full Duplex In full duplex flow control ADM5120 follows IEEE 802 3x standards If a PAUSE frame is received from a certain port it will stop the port transmission of p...

Page 34: ...d ports ADM5120 provides the VLAN MAC address function if the packet is assigned with the VLAN address as its destination MAC address then this packet will be forwarded to the CPU via DMA For example...

Page 35: ...24 0 Controlled by CPU except Own bit Bit Bit 31 Bit 24 0 Remark Type control Function buffer2_enable buffer2_address 24 0 Controlled by CPU Bit Bit 10 0 Remark Type control Function buffer1_length 10...

Page 36: ...g example buffer 1 size 14 buffer 2 disable the pkt length 60 or 64 without CRC padding Force desti port 5 0 the packet needs force forwarding to designated ports and it is the highest priority of rou...

Page 37: ...uffer2 has a enable bit to control whether the address is valid or not The buffer2 size must be larger than the remaining data If buffer2 is disabled and buffer1 has not enough space then the remainin...

Page 38: ...he AHB master interface and slave interface Host can program the USB Host controller operational register via the AHB slave interface The DMA units within the USB Host controller will act as bus maste...

Page 39: ...d and Resume 3 4 5 DPLL The DPLL block is a digital phase lock loop for extracting clock and data from the USB bus 3 4 6 Memory BIST The Memory BIST block is used for testing TFIFO and RFIFO In this m...

Page 40: ...10 7 EN Endpoint number of the current USB function 6 0 FA Function address of the current USB device DWORD 1 Tail Transfer Descriptor Bit Description 31 4 Starting address of the tail transfer descr...

Page 41: ...Toggle bit Data toggle bit This field is used for data PID value 24 when 0 use togglecarry bit in ED as the PID when 1 use but 23 as the toggle bit 23 toggle value 22 21 DIR These bits indicate this...

Page 42: ...transfer descriptors the software can specify the descriptor format Isochronous or none Isochronous direction speed and data toggle bit If there is any isochronous or periodic data that needs to be t...

Page 43: ...data 32 byte packet C framedata 200 byte Nth Frame DMA Descriptor Chain SOF send by host N 1th Frame pkt A 512B pkt B 128B ISO OUT ISO IN pkt C 64B A C K IN S O F pkt D 32B A C K OUT TD Tail ED descr...

Page 44: ...erval between the current Interrupt transaction and the next one Frame_Interval is calculated by the following formula Frame_Internal Interrupt service period 1 ADMtek Inc 3 16 The transfer of interru...

Page 45: ...OUT ED 2 INT IN ED 3 Next ED Token Data or handshake send by host Data or handshake send by device Prior ED TD Tail 0 Frame Number 1 Interval 2 buffer length 64 Byte buffer length 64 Byte buffer leng...

Page 46: ...0 MPMC USB 0x1160 0000 0x11A0 0000 MIPS 0x11C0 0000 reserved 0x1200 0000 switch 0x1220 0000 0x1240 0000 reserved reserved 0x1260 0000 0x1FC0 0000 SRAM_0 0x2000 0000 reserved boot address 4M byte 0x128...

Page 47: ...ation as byte access address 20 0 max size 2M bytes 16 bit access address 21 1 shift A0 out max size 4M bytes 32 bit access address 22 2 shift A0 A1 out max size 8M bytes use DQM to select the bytes P...

Page 48: ...2 PCI INT2 7 PCI 1 PCI INT1 6 PCI 0 PCI INT0 5 Intx_1 Internal interrupt 1 refer to GPIO 4 is the source 4 Intx_0 Internal interrupt 0 refer to GPIO 2 is the source 3 USB USB interrupt source 2 UART1...

Page 49: ...no effect 0 31 10 RO Reserved Not Applicable 0 4 2 6 IRQ_enable_clear offset 0xc0 Bits Type Name Description Initial value 9 0 RW IRQ_enable_clear 7 0 The clear bits of the IRQ_enable Writing 1 clear...

Page 50: ...s Type Name Initial value 9 0 RW IRQ_test_source 9 0 the test data for the IRQ_raw_status 0 31 10 Reserved Not Applicable 4 2 11 IRQ_source_sel offset 0x20 Bits Type Name Initial value 0 RW IRQ_source...

Page 51: ...W 4 10 Port_conf1 0x2c RW 4 11 Port_conf2 0x30 RW 4 11 Reserved 0x34 4 12 Reserved 0x38 4 12 Reserved 0x3c 4 13 VLAN_GI 0x40 RW 4 13 VLAN_GII 0x44 RW 4 13 Send_trig 0x48 RW 4 13 Srch_cmd 0x4c RW 4 13...

Page 52: ...xDc RW 4 24 send_Hwaddr 0xE0 RO 4 24 send_Lwaddr 0xE4 RO 4 24 receive_Hwaddr 0xE8 RO 4 24 Receive_Lwaddr 0xEc RO 4 24 Timer_int 0xF0 RW 4 24 Timer 0xF4 RW 4 25 Reserved 0xF8 4 25 Reserved 0xFc 4 25 po...

Page 53: ...t_done offset 0x08 Bits Type Name Description Initial value 0 RW Reserved 1 the software boot process is done and the address table can return to switch controller 4 4 3 SWReset offset 0x0c Note Whene...

Page 54: ...M 22 RO Icache_portion For debugging purpose of embedded SRAM 31 23 Reserved Not Applicable 4 4 6 PHY_St offset 0x14 Bits Type Name Description Initial value 4 0 RO Link PHY Link 1 up 0 down 5 RO MII_...

Page 55: ...de 110 111 reserved 001 512Kbyte 010 1Mbyte default 011 2Mbyte 100 4Mbyte 010 15 11 Reserved Not Applicable 18 16 RW SRAM1_size 000 disable default 001 512Kbyte 010 1Mbyte 011 2Mbyte 100 4Mbyte 101 8M...

Page 56: ...cket jam then one no jam 1010 21 20 RW BP_mode Back pressure mode 00 disable 01 BP jam the jam number is set by BP_num 10 BP jamALL jam packet until the BP condition is released default 11 BP carrier...

Page 57: ...ackets from port s forward to CPU 1 no send unknown packet from the port0 to port5 to CPU 15 Reserved Not Applicable 21 16 RW DisMC_port Disable multicast packets from port s forward to CPU 1 no send...

Page 58: ...akcets SA need match otherwise discard the packets Note 1 set Dis_Learn and SA_secured at the same time then only forward the packets with the SA and port number matched 2 2 set SA_secured only then n...

Page 59: ...in the dumb mode set to 1 0 8 RW TXC_check check the MII port TXC period if more than 400us then disable MII port 1 disable check TXC only for 10 100M default 0 enable check 1 10 9 RW Config_early_rdy...

Page 60: ...Applicable 4 4 18 VLAN_GII offset 0x44 Bits Type Name Description Initial value 6 0 RW VLAN4 VLAN group 4 the ports in VLAN group4 0000000 0000000 7 Reserved Not Applicable 14 8 RW VLAN5 VLAN group 5...

Page 61: ...offset 0x54 Bits Type Name Description Initial value 31 0 RO MAC_srch1 MAC address 47 16 4 4 23 MAC_wt0 offset 0x58 Bits Type Name Description Initial value 0 RW wtMAC_cmd MAC address write command 1...

Page 62: ...dth control 27 Reserved Not Applicable 30 28 RW P3rx_bwcntl Port3 receive bandwidth control 31 Reserved Not Applicable 4 4 26 BW_cntl1 offset 0x64 Bits Type Name Description Initial value 2 0 RW P4tx_...

Page 63: ...working Drop1_set threshold 137 x 2 274 4 4 30 adj_port_th offset 0x74 Bits Type Name Description Initial value RW adj_port_th_H per_port guaranteed normal priority pkt 3 blocks 7 4 RW adj_port_th_L...

Page 64: ...12 RW LFAILTM Recommend polarity link fail timer select Default 00 2sec 3 4 8 sec 00 14 RW INTCHKEN Recommend polarity LIU LID interval check 1 15 RW CBDETEN Recommend cable broken detect enable 0 16...

Page 65: ...ap1 offset 0x94 Bits Name Description Initial value 31 0 RW TOS_map1 TOS_bit_map 64 32 Type 4 4 39 Custom_pri1 offset 0x98 Bits Type Name Description Initial value RW Custom_en Enable custom packet ch...

Page 66: ...gth Port 4 cable broken length 18 RO P4_cbbrk Port 4 cable broken 19 Reserved Not Applicable 20 RW volt23 1 10BaseT voltage 2 3V 0 2 2V default 0 21 RW rom_code25 1 fix the ROM code to 2 5V 0 2 2V def...

Page 67: ...l port 4 4 45 Int_st offset 0xB0 Note All bits are write 1 clear Bits Type Description Initial value 0 RW send_H_done DMA send one high priority packet to switch 1 RW send_L_done DMA send one normal p...

Page 68: ...d Not Applicable 4 4 46 Int_mask offset 0xB4 Note 1 mask the interrupt Bits Type Name Description Initial value RW M_send_H_done 1 RW M_send_L_done 2 RW M_rx_H_done 3 RW M_rx_L_done 4 RW M_H_Descripto...

Page 69: ...ble Initial value 4 4 49 Watchdog0 offset 0xC0 Bits Type Name Description Initial value 14 0 RW Watchdog0_tmr Watchdog timer count up timer mask able write clear unit 10ms If reach timer set mean time...

Page 70: ...escription Initial value 7 0 RO Swap_dout Swap_dout 7 0 Swap_din 31 24 15 8 RO Swap_dout Swap_dout 15 8 Swap_din 23 16 23 16 RO Swap_dout Swap_dout 23 16 Swap_din 15 8 31 24 RO Swap_dout Swap_dout 31...

Page 71: ...RO port_sel The descriptor WORKING address of CPU_to_SW normal priority 31 25 Reserved Not Applicable 4 4 59 receive_Hwaddr offset 0xE8 Bits Type Name Description Initial value receive_HWaddr The desc...

Page 72: ...0 the input value when programmed in input mode 31 15 Reserved Not Applicable Note port0 LED 2 0 pin 164 165 166 configuration register 4 4 66 port1_LED offset 0x104 Bits Type Name Description Initia...

Page 73: ...nitial value 3 0 RW p4_LED0 port4 LED 0 state default 1001 link activity 1001 7 4 RW p4_LED1 port4 LED 1 state default 0101 speed 0101 11 8 RW p4_LED2 port4 LED 2 state default 1010 duplex col 1010 14...

Page 74: ...rbitration control Both modes 0 Receive Transmit 1 1 1 Receive Transmit 0 3 R W SW_RESET Software reset Both modes Setting this bit resets the device controller to its initial state This bit is auto c...

Page 75: ...t is set when software set one to SW_INT_REQ 0x00 and is cleared after software writes one to this bit 0 30 R W1 C FATAL_INT Fatal interrupt Device mode Reserved Host mode 1 Fatal system bus error occ...

Page 76: ...rame interval offset 0x18 Bits Type Name Description Initial value 13 0 R W FM_INTERVAL Frame interval This specifies the interval between two consecutive SOFs in bit times The nominal value is set to...

Page 77: ...e loads the content with the FM_INTERVAL of and uses the updated value from the next SOF 0 30 RO Reserved Not Applicable 0 31 R W FM_REMAININ G_TOG FrameRemaining toggle This bit is loaded from the FM...

Page 78: ...or per port switching 0 Ports are power switched 1 Ports are always powered on when the HC is powered on 0 10 R W OCPM OverCurrent protect Mode This bit describes how the overcurrent status for the R...

Page 79: ...is implemented this bit is always 0 0 26 R W LPSC Local power switch change read this bit is always read as 0 write SetGlobalPower In global power mode PSM 0 This bit is written to 1 to turn on power...

Page 80: ...his bit cannot be set when CCS is cleared This bit is also set if not already at the completion of a port reset when RSC is set or port suspend when SSC is set 0 port is disabled 1 port is enabled wri...

Page 81: ...eset is completed this bit is cleared when PRSC is set This bit cannot be set if CCS is cleared 0 port reset signal is not active 1 port reset signal is active write SetPortReset The HCD sets the port...

Page 82: ...et whenever a connect or disconnect event occurs The HCD writes a 1 to clear this bit Writing a 0 has no effect If CCS is cleared when a SPR SPE or SPS write occurs this bit is set to force the driver...

Page 83: ...port reset is not complete 1 port reset is complete 0 31 21 RO Reserved Not Applicable 0 4 6 13 Host Descriptor Head Starting Address offset 0x80 Bits Type Name Description Initial value 3 0 RO Reser...

Page 84: ...s 0 1 2 3 200h 220h 240h 260h MPMCStaticConfig 0 1 2 3 204h 224h 244h 264h MPMCStaticWaitWen 0 1 2 3 208h 228h 248h 268h MPMCStaticWaitOen 0 1 2 3 20Ch 22Ch 24Ch 26Ch MPMCStaticWaitRd 0 1 2 3 210h 230...

Page 85: ...ip select 4 reset value on nPOR On power on reset chip select 1 is mirrorred to both chip select 0 and chip select 1 and chip 4 memory areas Clearing the M bit enables chip select 0 and chip select 4...

Page 86: ...e The value of the endian bit on power on reset nPOR is determined by the MPMCBIGENDIAN signal This value can be overridden by software This field is unaffected by the AHB reset HRESETn 0 8 R W CLK Cl...

Page 87: ...Reserved Read undefined must be written as zeros 13 R W DP Low power SDRAM deep sleep mode 0 normal operation reset value on nPOR 1 enter deep power down mode 0 31 14 Reserved Read undefined must be...

Page 88: ...et 03Ch Bit Type Name Initial Value R W tAPR 0x0 to 0xE n 1 clock cycle 0xF 16 clock cycles reset value on nPOR 0xF 31 4 Reserved Read undefined must be written as zeros Descriptions 3 0 Last data out...

Page 89: ...cycles 4 7 15 MPMC Dynamic XSR register offset 050h Bit Type Name Descriptions Initial Value 4 0 R W tXSR Exit self refresh to active command period 0x0 to 0x1E n 1 clock cycle 0x1F 32 clock cycles re...

Page 90: ...Read undefined must be written as zeros 4 3 R W MD Memory device 00 SDRAM reset value on nPOR 01 low power SDRAM 10 11 reserved 00 6 5 Reserved Read undefined must be written as zeros 12 7 R W AM Add...

Page 91: ...efined must be written as zeros 26 R W NB Number of banks 0 two banks reset value on nPOR 1 four banks 0 27 Reserved Read undefined must be written as zeros 29 28 R W RW Row width 00 11 bit reset valu...

Page 92: ...ADM5120 Register Description ADMtek Inc 4 45...

Page 93: ...0 1 2 3 register Note offset 200h 220h is for F_CS1_N and F_CS0_N respectively ADMtek Inc 4 46 Bit Type Name Descriptions Initial Value 1 0 R W MW Memory width 00 8bit 01 16bit 10 32bit 11 reserved Th...

Page 94: ...mode memory devices are not supported 4 7 22 MPMC Static Wait Wen 0 1 2 3 register Note offset 200h 220h 240h is for SMC_CSZ0 SMC_CSZ1 and SMC_CSZ2 respectively Bit Name Descriptions 3 0 R W WAITWEN W...

Page 95: ...D 1 x tHCLK 4 7 25 MPMC Static Wait Page 0 1 2 3 register Note offset 200h 220h 240h is for SMC_CSZ0 SMC_CSZ1 and SMC_CSZ2 respectively Bit Name Descriptions Initial Value 4 0 R W WAITPAGE Asynchronou...

Page 96: ...urnaround time is WAITTURN 1 x tHCLK 4 7 28 Conceptual MPMC Additional Peripheral ID register Bit Type Name Descriptions Initial Value 7 0 R Configuration1 Additional peripheral configuration informat...

Page 97: ...MPMC PeriphID0 register offset FE0h Bit Type Name Descriptions Initial Value 7 0 R PartNumber0 These bits read back as 0x72 72 31 8 Reserved Read undefined must be written as zeros Note The MPMCPeriph...

Page 98: ...1 yes For PL172 this field is set to 1 Reserved Read undefined must be written as zeros Descriptions 2 0 R Indicates the number of AHB slave ports 011 6 AHB slave port 5 3 R 1 31 8 Note The MPMCPeriph...

Page 99: ...fined must be written as zeros 4 8 UART Registers 4 8 1 Remap and Pause Controller Registers Table 4 3 Remap and Pause Controller Registers Summary Offset Name Descriptions 00h UART data register UART...

Page 100: ...al Value 4 8 4 UART line control register high byte offset 08h ADMtek Inc 4 53 Bit Type Name Descriptions Initial Value 0 R W BRK Send Break If this bit is set to 1 a low level is continually output o...

Page 101: ...d rate divisor These bits are cleared to 0 on reset 0 Type 4 8 6 UART line control register low byte offset 10h Bit Type Name Descriptions Initial Value R W BAUD DIVLS Least significant byte of baud r...

Page 102: ...ents occurs 1 if the FIFOs are enabled and the transmit FIFO is at least half empty then the transmit interrupt is asserted HIGH It is cleared by filling the transmit FIFO to more than half full 2 if...

Page 103: ...ister RO TXFE Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H register If the FIFO is disabled this bit is set when the transmit holding register is em...

Page 104: ...upt is asserted 0 Reserved Not Applicable 7 W UARTICR A write to this register clears the modem status interrupt regardless of the value written Bit 0 This bit is set to 1 if the UARTRTINTR receive in...

Page 105: ...Specifications Parameter Description Condition Min Typical Max Units Vcc Supply Voltage 1 7 1 8 1 9 V Vcc Supply Voltage I O 3 0 3 3 3 6 V Icc Power Supply Vcc 1 8V mA Power Supply I O Vcc 3 3V mA Vil...

Page 106: ...s command address setup delay time in active stage P Tah command address hold delay time in active stage P Tws command address setup delay time in write stage P Twh command address hold delay time in...

Page 107: ...ADM5120 Electrical Specification Active Command SCLK SDC_CSZ 0 SDC_RASZ SDC_CASZ SDC_W EZ XA 14 0 addr Tck Tas Tah ADMtek Inc 5 3 Figure 5 2 Active Command...

Page 108: ...SDC_W EZ XA 14 0 XD 31 0 data1 data2 data3 data4 addr SDC_DQM 3 0 4 b0000 Tck Tws Twh Figure 5 3 Write Command Read Command SCLK SDC_CSZ 0 SDC_RASZ SDC_CASZ SDC_WEZ XA 14 0 XD 31 0 data1 data2 data3 d...

Page 109: ...a ROM FLASH External Memory Two Output enable delay state Read Timing CLK_OUT ADDR 19 0 DATA 31 0 F_CSX_N F_OE_N 2T 3T 1T Notes T is the period of CLK_OUT 11 5ns 87 5Mhz tDSU Item Description Min Typ...

Page 110: ...g CLK_OUT ADDR 19 0 DATA 31 0 F_CSX_N WE_N Address Data ROM FLASH External Memory Two Write enable delay state WriteTiming CLK_OUT ADDR 19 0 DATA 31 0 F_CSX_N WE_N 1T 1T 1T 3T 2T 3T Notes T is the per...

Page 111: ...ADM5120 Packaging Chapter 6 Packaging 6 1 Ball Grid Array BGA 324 pin Note Scale mm ADMtek Inc 6 1...

Page 112: ...6 2 Plastic Quad Flat Pack PQFP 208 pin Note Scale mm MILLIMETER INCH Symbol MIN NOM MAX MIN NOM MAX b 0 17 0 20 0 27 0 007 0 008 0 011 e 0 50 BSC 0 020 BSC D2 25 50 1 004 E2 25 50 1 004 aaa 0 25 0 0...

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