ADM5120
Register Description
4.4.47 GPIO_conf0, offset 0xB8
Bits
Type Name
Description
Initial value
7:0
RW
in_out0
GPIO[7:0] input or output
→
1: input
15:8 RO
in_value0
GPIO[7:0] input value if in the input mode
23:16 RW out_en0
GPIO[7:0] output enable if in the output mode
→
0:
input (default)
31:24 RW
out_value0
GPIO[7:0] output value if in the output mode and
enable
4.4.48 GPIO_conf2, offset 0xBc
Bits
Type Name
Description
3:0
Reserved
Not
Applicable
4
WO
en_csx_intx
1: enable wait control, GPIO[0], for the CSX interface
0: disable
5
WO
en_csx1_intx1
Enable CSX1, INTX1 in GPIO[3:4]
→
0: disable
6
WO
en_wait
Enable CSX, INTX in GPIO[1:2]
→
0: disable
31:7
Reserved
Not
Applicable
Initial value
4.4.49 Watchdog0, offset 0xC0
Bits
Type Name
Description
Initial value
14:0 RW
Watchdog0_tmr Watchdog timer: count up timer, mask-able, write clear,
unit 10ms. If reach timer set mean time up and keep the
counter until write-clear by software, maximum 327sec.
15 Reserved
Not
Applicable
30:16 RW Watchdog0_tmr_s
et
Watchdog timer set: the time out setting of timer, if
timer set is equal to timer, then it mean timer is expired.
Maximum 32767
31
RW
Watchdog0_reset_
en
Watchdog timer trigger reset:
0: disable,
1: reset the whole chip, if watchdog timer expired
4.4.50 Watchdog1, offset 0xC4
ADMtek Inc.
4-22
Bits
Type Name
Description
Initial value
14:0 RW
Watchdog1_tmr Watchdog1 timer: Count up timer, mask-able, write
clear, unit 10ms. If reach timer set mean time up and
keep the counter until write-clear by software,
maximum 327sec.
15 Reserved
Not
Applicable