ADM5120
Function Description
– Buffer1 has length information, if packet size is larger than buffer1 size,
then get the rest of the data from buffer2.
– Buffer address must be valid when a descriptor belongs to a switch, the
switch engine will not check the address status.
– Buffer2 has an enable bit to control whether the address is valid or not.
– If the buffer2 is disabled and buffer1 is not long enough, then the
remaining data will not be padded “0” to make the packet meet 64-bytes
standard.
•
append_chksum: need to append the IP (0x0800) and PPPoE (0x8864) packets IP-
checksum by hardware
– The packet checksum field must be pre-filled with all “0”’s
•
Packet length: the packet length in bytes, excluding CRC if CRC is not padded. (See
the register, CPUp_conf)
– auto-padding: the engine can automatically pad the “0” into the packet
which data size is less than 60B (or 64). The setting example: buffer 1
size=14, buffer 2 disable, the pkt length=60 (or 64 without CRC padding).
•
Force desti-port[5:0]: the packet needs force forwarding to designated ports, and it is
the highest priority of routing. If forced, then ignore the routing and To_VLAN flag.
•
To_VLAN[5:0]: the bit-map, the packet forwards to the designated VLAN group.
Use this flag to control the packets to LAN, WAN, or HPNA ports.
3.3.15 Receive descriptors content
If switch sends the packet to CPU, either LAN or WAN, then the ‘receive descriptors’ are
used as follows:
Bit
Bit[31]
Bit[28]
Bit[24:0] Remark
Type
control
Function Own bit ring end flag
buffer1_address
[24:0]
Controlled by CPU
except Own-bit
Bit
Bit[31]
Bit[24:0]
Remark
Type
control
Function
buffer2_enable
buffer2_address
[24:0]
Controlled by CPU
Bit
Bit[10:0]
Remark
Type
control
Function
buffer1_length
[10:0]
Controlled by CPU
Bit [26:16] [14:12] [5:4]
[3]
[2] [1:0]
remark
Type packet
status
functio
n
pkt-
length[10:
0]
Source
port
number
00:
UC
01: MC
10: BC
IP
checksum
fail
VLAN
tag
00: 0x0800
01: 0x8864
11, 10: reserved
updated
by
switch
ADMtek Inc.
3-8