ADM5120
Register Description
Bit # Type Name
Descriptions
Initial Value
memory controller enters the low-power or disabled
mode cleanly:
0 = MPMC is idle (reset value on nPOR, and HRESETn)
1 = MPMC is busy performing memory transactions.
1
R
S
Write buffer status: this read only bit enables the
PrimeCell MPMC to enter low-power mode or disabled
mode cleanly.
0 = write buffers empty (reset value on nPOR)
1 = write buffers contain data.
0
2 R SREFACKA Self-refresh
acknowledge: this read only bit indicates the
operating mode of the MPMC.
0 = normal mode (reset value on nPOR)
1 = self-refresh acknowledge.
0
31:3
Reserved
Not
Applicable
4.7.4 MPMC Config register, offset 008h
Bit # Type Name
Descriptions
Initial Value
0 R/W
N
Endian
mode:
0 = little-endian mode
1 = big-endian mode.
The value of the endian bit on power-on-reset (nPOR) is
determined by the MPMCBIGENDIAN signal.
This value can be overridden by software. This field is
unaffected by the AHB reset (HRESETn).
0
8
R/W CLK
Clock ratio: HCLK:MPMCCLKOUT[3:0] ratio.
0 = 1:1 (reset value on nPOR)
1 = 1:2.
0
7:1
Reserved
Read undefined, must be written as zeros.
31:9
Reserved
Read undefined, must be written as zeros.
4.7.5 MPMC Dynamic Control register, offset 020h
Bit # Type
ADMtek Inc.
4-39
Name
Descriptions
Initial Value
0
R/W CE
0
Dynamic memory clock enable:
0 = clock enable of devices are deasserted to save power
(reset value on nPOR)
1 = all clock enables are driven HIGH continuously.
1
R/W CS
Dynamic memory clock control:
0 = MPMCCLKOUT stops when all SDRAMs are idle
and during self-refrsh mode
1 = MPMCCLKOUT runs continuously (reset value on
nPOR).
When clock control is LOW the output clock
MPMCCLKOUT is stopped when there are no SDRAM
transactions. The clock is also stopped during self-
1