ADMtek ADM5120, Datasheet, Page: 63 / 112

ADM5120 Register Description
14 RW RD_cmd Read command, self_clear
15 Reserved Not Applicable
31:16 RW WT_data The data be written into the PHY
4.4.28 PHY_cntl1, offset 0x6c
Bits Type Name Description Initial value
0 RO WT_done Write operation is done, read_clear
1 RO RD_rdy Read operation is complete and data is ready, read_clear
15:2 Reserved Not Applicable
31:16 RO RD_data The read data
4.4.29 FC_th, offset 0x70
Bits Type Name Description Initial value
7:0 RW Drop2_set Switch drop2 set threshold
→
106 free blocks
15:8 RW Drop2_rls Switch drop2 release threshold
→
134 free blocks
24:16 RW FC_set Switch flow control set threshold
→
220 free blocks
31:25 Reserved Not Applicable
Note:
The working global thresholds = (register value) * 2, The Drop1_set[7:0] threshold default value =
137 blocks, The default working Drop1_set threshold = 137 x 2 =274.
4.4.30 adj_port_th, offset 0x74
Bits Type Name Description Initial value
RW adj_port_th_H per_port guaranteed normal priority pkt
→
3 blocks
7:4 RW adj_port_th_L per_port guaranteed high priority pkt
→
3 blocks
15:8 Reserved Not Applicable
24:16 RW FC_rls Switch flow control release threshold
→
268 free blocks
31:25 Reserved Not Applicable
3:0
4.4.31 Port_th, offset 0x78
Bits Type Name Description Initial value
7:0 RW per_port_th per port buffer threshold
→
13 occupied blocks
15:8 RW CPU_th CPU port buffer threshold
→
48 occupied blocks
23:16 RW CPU_hold_th the CPU hold threshold for all ports
→
default 120 free
block
31:24 RW CPU_rls_th the CPU hold release threshold
→
default 132 free block
Note:
Suggestion value is 0xE8DC1818h.
4.4.32 PHY_cntl2, offset 0x7c
ADMtek Inc. 4-16
Bits Type Name Description Initial value
4:0 RW Auto-negotiation Auto-negotiation enable. 1: Enable
9:5 RW Speed Speed control. 1: 100M 0: 10M
14:10 RW Duplex Duplex control. 1: Full 0: Half