Acer Altos 9100 Series, User Manual

Page: 53 / 162

AcerAltos 9100 Series User’s Guide
3-12
3.3.2 External Cache (CPU Cache)
This parameter enables or disables the second-level cache memory.
Cache Scheme
This parameter allows you to select Write back or Write through for the cache
mode. Write back updates the cache but not the memory when there is a write
instruction. It updates the memory only when there is an inconsistency between
the cache and the memory. Write through updates both the cache and the
memory whenever there is a write instruction.
3.3.3 ECC/Parity Mode Selection
This parameter allows you to select ECC, Parity, or Disabled . The ECC option
allows single-bit error detection and automatic correction. The automatic
correction depends on the setting of the parameter Operation of ECC. See section
3.3.4 for details.
ECC also detects multiple-bit errors but does not correct them. Instead, it issues a
non-maskable interrupt (NMI) signaling the operating system of the multiple-bit
error detection.
The Parity option allows parity check. If it detects any parity errors, it sets up the
parity error flag in the chipset. This signals the operating system of the parity
error detection.
Fast-page mode DIMMs with parity support both ECC and parity mode. EDO
DIMMs with parity support only ECC mode.
Both the ECC and parity check features require
parity DIMMs. You must disable this parameter
if you installed DIMMs without parity.