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List of Figures
1-1
Functional Block Diagram
.................................................................................................
2-1
ARM Subsystem Block Diagram
.........................................................................................
5-1
Clocking Architecture
6-1
PLLC1 Configuration
6-2
PLLC2 Configuration
6-3
Clock Ratio Change and Alignment with Go Operation
...............................................................
6-4
Peripheral ID Register (PID)
..............................................................................................
6-5
PLL Control Register (PLLCTL)
..........................................................................................
6-6
PLL Multiplier Control Register (PLLM)
.................................................................................
6-7
PLL Pre-Divider Control Register (PREDIV)
............................................................................
6-8
PLL Controller Divider 1 Register (PLLDIV1)
...........................................................................
6-9
PLL Controller Divider 2 Register (PLLDIV2)
...........................................................................
6-10
PLL Controller Divider 3 Register (PLLDIV3)
...........................................................................
6-11
PLL Post-Divider Control Register (POSTDIV)
.........................................................................
6-12
Bypass Divider Register (BPDIV)
........................................................................................
6-13
PLL Controller Command Register (PLLCMD)
.........................................................................
6-14
PLL Controller Status Register (PLLSTAT)
.............................................................................
6-15
PLL Controller Clock Align Control Register (ALNCTL)
...............................................................
6-16
PLLDIV Ratio Change Status (DCHANGE)
.............................................................................
6-17
Clock Enable Control Register (CKEN)
.................................................................................
6-18
Clock Status Register (CKSTAT)
........................................................................................
6-19
SYSCLK Status Register (SYSTAT)
.....................................................................................
6-20
PLL Controller Divider 4 Register (PLLDIV4)
...........................................................................
7-1
Power and Sleep Controller (PSC)
......................................................................................
7-2
Power Domain and Module Topology
...................................................................................
7-3
Peripheral Revision and Class Information Register (PID)
...........................................................
7-4
Interrupt Evaluation Register (INTEVAL)
................................................................................
7-5
Module Error Pending Register 0 (mod 0 - 31) (MERRPR0)
.........................................................
7-6
Module Error Pending Register 1 (mod 32-41) (MERRPR1)
.........................................................
7-7
Module Error Clear Register 0 (mod 0-31) (MERRCR0)
..............................................................
7-8
Module Error Clear Register 1 (mod 32-41) (MERRCR1)
............................................................
7-9
Power Error Pending Register (PERRPR)
..............................................................................
7-10
Power Error Clear Register (PERRCR)
.................................................................................
7-11
External Power Control Pending Register (EPCPR)
..................................................................
7-12
External Power Control Clear Register (EPCCR)
......................................................................
7-13
Power Domain Transition Command Register (PTCMD)
.............................................................
7-14
Power Domain Transition Status Register (PTSTAT)
.................................................................
7-15
Power Domain Status n Register (PDSTATn)
..........................................................................
7-16
Power Domain Control n Register (PDCTLn)
..........................................................................
7-17
Module Status n Register (MDSTATn)
..................................................................................
7-18
Module Control n Register 0-41 (MDCTLn)
.............................................................................
8-1
AINTC Functional Diagram
...............................................................................................
8-2
Interrupt Entry Table
8-3
Immediate Interrupt Disable / Enable
....................................................................................
8-4
Delayed Interrupt Disable
.................................................................................................
8-5
Interrupt Status of INT[31:0] (if mapped to FIQ)
.......................................................................
8-6
Interrupt Status of INT[63:32] (if mapped to FIQ)
......................................................................
8-7
Interrupt Status of INT[31:0] (if mapped to IRQ)
.......................................................................
8-8
Interrupt Status of INT[31:0] (if mapped to IRQ)
.......................................................................
8-9
Fast Interrupt Request Entry Address Register (FIQENTRY)
........................................................
8-10
Interrupt Request Entry Address Register (IRQENTRY)
..............................................................
8-11
Interrupt Enable Register 0 (EINT0)
....................................................................................
8
List of Figures
SPRUFX7 – July 2008